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zephyr/tests/arch/riscv/fpu_sharing/prj.conf

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tests: riscv: test FPU sharing access behavior The RISC-V FPU context switching code is intricate and sometimes subtle. Here's a test that exercizes various code paths to ensure they work as intended, and to confirm that the target hardware does behave as expected too. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-01-28 08:30:57 +08:00
CONFIG_ZTEST=y
CONFIG_FPU=y
CONFIG_FPU_SHARING=y
CONFIG_IRQ_OFFLOAD=y
CONFIG_MP_MAX_NUM_CPUS=1