2017-07-01 02:48:58 +08:00
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#include "skeleton.dtsi"
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#include "mem.h"
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/ {
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cpus {
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2017-07-27 02:20:06 +08:00
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#address-cells = <1>;
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#size-cells = <0>;
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2017-07-01 02:48:58 +08:00
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cpu@0 {
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2017-07-22 00:02:36 +08:00
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device_type = "cpu";
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2017-07-01 02:48:58 +08:00
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compatible = "intel,quark";
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2017-07-22 00:02:36 +08:00
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reg = <0>;
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2017-07-01 02:48:58 +08:00
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};
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};
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flash0: flash@00180000 {
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reg = <0x00180000 DT_FLASH_SIZE>;
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};
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sram0: memory@00280000 {
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2017-07-21 23:57:58 +08:00
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device_type = "memory";
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2017-07-20 21:21:12 +08:00
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compatible = "mmio-sram";
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2017-07-01 02:48:58 +08:00
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reg = <0x00280000 DT_SRAM_SIZE>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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rtc: rtc@b0000400 {
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compatible = "intel,qmsi-rtc";
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reg = <0xb0000400 0x400>;
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clock-frequency = <32768>;
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};
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uart0: uart@b0002000 {
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compatible = "intel,qmsi-uart";
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reg = <0xb0002000 0x400>;
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label = "UART_0";
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status = "disabled";
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};
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uart1: uart@b0002400 {
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compatible = "intel,qmsi-uart";
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reg = <0xb0002400 0x400>;
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label = "UART_1";
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status = "disabled";
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};
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gpio: gpio@b000c000 {
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compatible = "intel,qmsi-gpio";
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reg = <0xb00c00 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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