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zephyr/dts/bindings/riscv/sifive,e24.yaml

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dts: bindings: riscv: Add sifive-e24 cpu Add sifive-e24 cpu binding. This introduce riscv,cpu binding to be used as riscv cpu base and riscv,sifive, which define specific properties for this vendor. Both are necessary to create the e24 core. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2021-08-03 09:32:23 +08:00
# Copyright (c) 2021 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
description: SiFive E24 Standard Core CPU
dts: bindings: riscv: Don't use riscv, prefix for vendor compat In 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings for sifive CPUs'), new compat strings for SiFive CPUs were added, but with riscv prefixes. Vendor-specific compats should just be prefixed with the vendor, so move that over here. Fixes: 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings for sifive CPUs') Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 01:42:00 +08:00
compatible: "sifive,e24"
dts: bindings: riscv: Add sifive-e24 cpu Add sifive-e24 cpu binding. This introduce riscv,cpu binding to be used as riscv cpu base and riscv,sifive, which define specific properties for this vendor. Both are necessary to create the e24 core. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2021-08-03 09:32:23 +08:00
dts: bindings: riscv: Don't use riscv, prefix for vendor compat In 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings for sifive CPUs'), new compat strings for SiFive CPUs were added, but with riscv prefixes. Vendor-specific compats should just be prefixed with the vendor, so move that over here. Fixes: 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings for sifive CPUs') Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 01:42:00 +08:00
include: sifive-common.yaml