95 lines
2.8 KiB
YAML
95 lines
2.8 KiB
YAML
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# Copyright (c) 2022 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: |
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The node has the 'pinctrl' node label set in MCUX SoC's devicetree. These
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nodes can be autogenerated using the MCUXpresso config tools combined with
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the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
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fields in a group select the pins to be configured, and the remaining
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devicetree properties set configuration values for those pins
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for example, here is an group configuring LPUART1 pins:
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group0 {
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pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx:,
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&iomuxc_uart4_txd_uart_tx_uart4_tx>;
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bias-pull-up;
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slew-rate = "slow";
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drive-strength = "x1";
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};
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This will select UART4_RXD as UART4 rx, and UART4_TXD as UART4 tx.
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Both pins will be configured with a slow slew rate, and minimum drive
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strength.
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Note that the soc level iomuxc dts file can be examined to find the possible
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pinmux options. Here are the affects of each property on the
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IOMUXC SW_PAD_CTL register:
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input-schmitt-enable: HYS=1
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bias-pull-up: PUE=1, PE=1
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bias-pull-down: PUE=0, PE=1
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drive-open-drain: ODE=1
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slew-rate: FSEL=<enum_idx>
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drive-strength: DSE=<enum_idx>
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input-enable: SION=1 (in SW_MUX_CTL_PAD register)
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If only required properties are supplied, the pin will have the following
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configuration:
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HYS=0,
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PE=0
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PUE=0
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ODE=0,
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SRE=<slew-rate>,
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DSE=<drive-strength>,
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SION=0,
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compatible: "nxp,imx8mp-pinctrl"
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include:
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- name: base.yaml
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- name: pincfg-node-group.yaml
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child-binding:
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child-binding:
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property-allowlist:
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- input-schmitt-enable
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- drive-open-drain
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- input-enable
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- bias-pull-up
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- bias-pull-down
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child-binding:
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description: iMX pin controller pin group
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child-binding:
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description: |
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iMX pin controller pin configuration node.
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properties:
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pinmux:
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required: true
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type: phandles
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description: |
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Pin mux selections for this group. See the soc level iomuxc DTSI file
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for a defined list of these options.
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drive-strength:
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required: true
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type: string
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enum:
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- "x1"
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- "x4"
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- "x2"
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- "x6"
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description: |
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Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
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00 X1- low drive strength
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01 X4- high drive strength
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10 X2- medium drive strength
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11 X6- max drive strength
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slew-rate:
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required: true
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type: string
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enum:
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- "slow"
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- "fast"
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description: |
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Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
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0 SLOW — Slow Frequency Slew Rate
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1 FAST — Fast Frequency Slew Rate
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