37 lines
709 B
YAML
37 lines
709 B
YAML
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# Copyright (c) 2021, Linaro ltd
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# SPDX-License-Identifier: Apache-2.0
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description: |
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PLL2 node binding for Connectivity line devices (STM32F105/STM32F107)
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Takes clk_hse as input clock, using prediv as prescaler.
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Each PLL as its own output clock.
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f(PLL2CLK) = f(PLL2IN) / PREDIV * PLLMUL --> PLL (System Clock)
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compatible: "st,stm32f105-pll2-clock"
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include:
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- name: st,stm32f105-pll-clock.yaml
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property-blocklist:
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- mul
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properties:
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mul:
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type: int
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required: true
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description: |
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PLL multiplication factor for output clock
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enum:
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- 8
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- 9
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- 10
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- 11
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- 12
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- 13
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- 14
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- 16
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- 20
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