2020-04-08 17:34:30 +08:00
|
|
|
/*
|
|
|
|
* Copyright 2020 Broadcom
|
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
|
|
*/
|
|
|
|
|
|
|
|
/ {
|
|
|
|
soc {
|
|
|
|
sram0: memory@400000 {
|
|
|
|
device_type = "memory";
|
|
|
|
reg = <0x00400000 0x80000>;
|
|
|
|
};
|
|
|
|
|
|
|
|
uart0: uart@40020000 {
|
|
|
|
compatible = "ns16550";
|
|
|
|
reg = <0x40020000 0x400>;
|
|
|
|
clock-frequency = <25000000>;
|
|
|
|
label = "CRMU_UART";
|
2022-06-15 19:59:22 +08:00
|
|
|
reg-shift = <2>;
|
2020-04-08 17:34:30 +08:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
uart1: uart@48100000 {
|
|
|
|
compatible = "ns16550";
|
|
|
|
reg = <0x48100000 0x400>;
|
|
|
|
clock-frequency = <100000000>;
|
|
|
|
label = "CCG_UART0";
|
2022-06-15 19:59:22 +08:00
|
|
|
reg-shift = <2>;
|
2020-04-08 17:34:30 +08:00
|
|
|
status = "disabled";
|
|
|
|
};
|
2020-05-08 17:55:07 +08:00
|
|
|
|
|
|
|
pl330: pl330@48300000 {
|
|
|
|
compatible = "arm,dma-pl330";
|
|
|
|
reg = <0x48300000 0x2000>,
|
|
|
|
<0x482f005c 0x20>;
|
|
|
|
reg-names = "pl330_regs",
|
|
|
|
"control_regs";
|
|
|
|
microcode = <0x63b00000 0x1000>;
|
|
|
|
dma-channels = <8>;
|
2020-10-28 01:55:01 +08:00
|
|
|
#dma-cells = <1>;
|
2021-02-15 12:33:10 +08:00
|
|
|
label = "DMA_0";
|
2020-05-08 17:55:07 +08:00
|
|
|
};
|
2020-04-08 17:34:30 +08:00
|
|
|
};
|
2020-05-04 15:27:13 +08:00
|
|
|
|
|
|
|
pcie {
|
|
|
|
#address-cells = <2>;
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
|
|
|
pcie0_ep: pcie@4e100000 {
|
|
|
|
compatible = "brcm,iproc-pcie-ep";
|
|
|
|
reg = <0x0 0x4e100000 0x0 0x2100>,
|
|
|
|
<0x0 0x50000000 0x0 0x8000000>,
|
|
|
|
<0x4 0x0 0x0 0x8000000>;
|
|
|
|
reg-names = "iproc_pcie_regs", "map_lowmem",
|
|
|
|
"map_highmem";
|
|
|
|
label = "PCIE_0";
|
2020-10-28 01:55:01 +08:00
|
|
|
dmas = <&pl330 0>, <&pl330 1>;
|
|
|
|
dma-names = "txdma", "rxdma";
|
2020-05-04 15:27:13 +08:00
|
|
|
};
|
2020-08-28 15:25:19 +08:00
|
|
|
|
|
|
|
paxdma: paxdma@4e100800 {
|
|
|
|
compatible = "brcm,iproc-pax-dma-v2";
|
2021-03-03 22:30:42 +08:00
|
|
|
label = "DMA_1";
|
2020-08-28 15:25:19 +08:00
|
|
|
reg = <0x0 0x4e100800 0x0 0x2100>,
|
|
|
|
<0x0 0x4f000000 0x0 0x200000>,
|
|
|
|
<0x0 0x4f200000 0x0 0x10000>;
|
|
|
|
reg-names = "dme_regs", "rm_ring_regs",
|
|
|
|
"rm_comm_regs";
|
|
|
|
dma-channels = <4>;
|
|
|
|
#dma-cells = <1>;
|
|
|
|
bd-memory = <0x63b00000 0x100000>;
|
|
|
|
scr-addr-loc = <0x200061f0>;
|
|
|
|
scr-size-loc = <0x200061f8>;
|
|
|
|
pcie-ep = <&pcie0_ep>;
|
|
|
|
};
|
2020-05-04 15:27:13 +08:00
|
|
|
};
|
2020-04-08 17:34:30 +08:00
|
|
|
};
|