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zephyr/include/drivers/sysapic.h

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apic : Refactor some macros into a header Moving few macros into a header file. Change-Id: I975e19ba518bd6184038d6c1715224be7190b3ad Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-05-07 11:56:24 +08:00
/*
* Copyright (c) 2016 Intel Corporation
*
license: Replace Apache boilerplate with SPDX tag Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 09:01:01 +08:00
* SPDX-License-Identifier: Apache-2.0
apic : Refactor some macros into a header Moving few macros into a header file. Change-Id: I975e19ba518bd6184038d6c1715224be7190b3ad Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-05-07 11:56:24 +08:00
*/
headers: Fix headers across the project Any word started with underscore followed by and uppercase letter or a second underscore is a reserved word according with C99. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-15 01:43:44 +08:00
#ifndef ZEPHYR_INCLUDE_DRIVERS_SYSAPIC_H_
#define ZEPHYR_INCLUDE_DRIVERS_SYSAPIC_H_
apic : Refactor some macros into a header Moving few macros into a header file. Change-Id: I975e19ba518bd6184038d6c1715224be7190b3ad Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-05-07 11:56:24 +08:00
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
#include <drivers/loapic.h>
apic : Refactor some macros into a header Moving few macros into a header file. Change-Id: I975e19ba518bd6184038d6c1715224be7190b3ad Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-05-07 11:56:24 +08:00
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
#define _IRQ_TRIGGER_EDGE IOAPIC_EDGE
#define _IRQ_TRIGGER_LEVEL IOAPIC_LEVEL
apic : Refactor some macros into a header Moving few macros into a header file. Change-Id: I975e19ba518bd6184038d6c1715224be7190b3ad Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-05-07 11:56:24 +08:00
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
#define _IRQ_POLARITY_HIGH IOAPIC_HIGH
#define _IRQ_POLARITY_LOW IOAPIC_LOW
apic : Refactor some macros into a header Moving few macros into a header file. Change-Id: I975e19ba518bd6184038d6c1715224be7190b3ad Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-05-07 11:56:24 +08:00
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
#ifndef _ASMLANGUAGE
x86: apic: don't include headers we don't need We were unnecessarily pulling in headers which resulted in kernel.h being pulled in, which is undesirable since arch/cpu.h pulls in these headers. Added integral type headers since we do need those. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-11-03 02:00:28 +08:00
#include <zephyr/types.h>
apic : Refactor some macros into a header Moving few macros into a header file. Change-Id: I975e19ba518bd6184038d6c1715224be7190b3ad Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-05-07 11:56:24 +08:00
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
#define LOAPIC_IRQ_BASE CONFIG_IOAPIC_NUM_RTES
#define LOAPIC_IRQ_COUNT 6 /* Default to LOAPIC_TIMER to LOAPIC_ERROR */
apic : Refactor some macros into a header Moving few macros into a header file. Change-Id: I975e19ba518bd6184038d6c1715224be7190b3ad Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-05-07 11:56:24 +08:00
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
/* irq_controller.h interface */
void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
Convert remaining code to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. This handles the remaining includes and kernel, plus touching up various points that we skipped because of include dependancies. We also convert the PRI printf formatters in the arch code over to normal formatters. Jira: ZEP-2051 Change-Id: Iecbb12601a3ee4ea936fd7ddea37788a645b08b0 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 23:55:34 +08:00
u32_t flags);
apic : Refactor some macros into a header Moving few macros into a header file. Change-Id: I975e19ba518bd6184038d6c1715224be7190b3ad Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-05-07 11:56:24 +08:00
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
int __irq_controller_isr_vector_get(void);
apic : Refactor some macros into a header Moving few macros into a header file. Change-Id: I975e19ba518bd6184038d6c1715224be7190b3ad Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-05-07 11:56:24 +08:00
jailhouse: add support for x2APIC mode for all LOAPIC accesses Besides the fact that we did not have that for the current supported boards, that makes sense for this new, virtualized mode, that is meant to be run on top of full-fledged x86 64 CPUs. By having xAPIC mode access only, Jailhouse has to intercept those MMIO reads and writes, in order to examine what they do and arbitrate if it's safe or not (e.g. not all values are accepted to ICR register). This means that we can't run away from having a VM-exit event for each and every access to APIC memory region and this impacts the latency the guest OS observes over bare metal a lot. When in x2APIC mode, Jailhouse does not require VM-exits for MSR accesses other that writes to the ICR register, so the latency the guest observes is reduced to almost zero. Here are some outputs of the the command line $ sudo ./tools/jailhouse cell stats tiny-demo on a Jailhouse's root cell console, for one of the Zephyr demos using LOAPIC timers, left for a couple of seconds: Statistics for tiny-demo cell (x2APIC root, x2APIC inmate) COUNTER SUM PER SEC vmexits_total 7 0 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_msr 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xapic 0 0 vmexits_xsetbv 0 0 Statistics for tiny-demo cell (xAPIC root, xAPIC inmate) COUNTER SUM PER SEC vmexits_total 4087 40 vmexits_xapic 4080 40 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_msr 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xsetbv 0 0 Statistics for tiny-demo cell (xAPIC root, x2APIC inmate) COUNTER SUM PER SEC vmexits_total 4087 40 vmexits_msr 4080 40 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xapic 0 0 vmexits_xsetbv 0 0 See that under x2APIC mode on both Jailhouse/root-cell and guest, the interruptions from the hypervisor are minimal. That is not the case when Jailhouse is on xAPIC mode, though. Note also that, as a plus, x2APIC accesses on the guest will map to xAPIC MMIO on the hypervisor just fine. Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
2017-10-12 05:17:12 +08:00
#ifdef CONFIG_JAILHOUSE_X2APIC
all: Update reserved function names Update reserved function names starting with one underscore, replacing them as follows: '_k_' with 'z_' '_K_' with 'Z_' '_handler_' with 'z_handl_' '_Cstart' with 'z_cstart' '_Swap' with 'z_swap' This renaming is done on both global and those static function names in kernel/include and include/. Other static function names in kernel/ are renamed by removing the leading underscore. Other function names not starting with any prefix listed above are renamed starting with a 'z_' or 'Z_' prefix. Function names starting with two or three leading underscores are not automatcally renamed since these names will collide with the variants with two or three leading underscores. Various generator scripts have also been updated as well as perf, linker and usb files. These are drivers/serial/uart_handlers.c include/linker/kobject-text.ld kernel/include/syscall_handler.h scripts/gen_kobject_list.py scripts/gen_syscall_header.py Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2019-03-09 05:19:05 +08:00
void z_jailhouse_eoi(void);
jailhouse: add support for x2APIC mode for all LOAPIC accesses Besides the fact that we did not have that for the current supported boards, that makes sense for this new, virtualized mode, that is meant to be run on top of full-fledged x86 64 CPUs. By having xAPIC mode access only, Jailhouse has to intercept those MMIO reads and writes, in order to examine what they do and arbitrate if it's safe or not (e.g. not all values are accepted to ICR register). This means that we can't run away from having a VM-exit event for each and every access to APIC memory region and this impacts the latency the guest OS observes over bare metal a lot. When in x2APIC mode, Jailhouse does not require VM-exits for MSR accesses other that writes to the ICR register, so the latency the guest observes is reduced to almost zero. Here are some outputs of the the command line $ sudo ./tools/jailhouse cell stats tiny-demo on a Jailhouse's root cell console, for one of the Zephyr demos using LOAPIC timers, left for a couple of seconds: Statistics for tiny-demo cell (x2APIC root, x2APIC inmate) COUNTER SUM PER SEC vmexits_total 7 0 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_msr 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xapic 0 0 vmexits_xsetbv 0 0 Statistics for tiny-demo cell (xAPIC root, xAPIC inmate) COUNTER SUM PER SEC vmexits_total 4087 40 vmexits_xapic 4080 40 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_msr 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xsetbv 0 0 Statistics for tiny-demo cell (xAPIC root, x2APIC inmate) COUNTER SUM PER SEC vmexits_total 4087 40 vmexits_msr 4080 40 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xapic 0 0 vmexits_xsetbv 0 0 See that under x2APIC mode on both Jailhouse/root-cell and guest, the interruptions from the hypervisor are minimal. That is not the case when Jailhouse is on xAPIC mode, though. Note also that, as a plus, x2APIC accesses on the guest will map to xAPIC MMIO on the hypervisor just fine. Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
2017-10-12 05:17:12 +08:00
#endif
x86: implement direct interrupts Change-Id: Icac461a361dde969f023e7aa11f0605a97a3c009 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-01-19 05:20:37 +08:00
static inline void __irq_controller_eoi(void)
{
#if CONFIG_EOI_FORWARDING_BUG
all: Update reserved function names Update reserved function names starting with one underscore, replacing them as follows: '_k_' with 'z_' '_K_' with 'Z_' '_handler_' with 'z_handl_' '_Cstart' with 'z_cstart' '_Swap' with 'z_swap' This renaming is done on both global and those static function names in kernel/include and include/. Other static function names in kernel/ are renamed by removing the leading underscore. Other function names not starting with any prefix listed above are renamed starting with a 'z_' or 'Z_' prefix. Function names starting with two or three leading underscores are not automatcally renamed since these names will collide with the variants with two or three leading underscores. Various generator scripts have also been updated as well as perf, linker and usb files. These are drivers/serial/uart_handlers.c include/linker/kobject-text.ld kernel/include/syscall_handler.h scripts/gen_kobject_list.py scripts/gen_syscall_header.py Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2019-03-09 05:19:05 +08:00
z_lakemont_eoi();
x86: implement direct interrupts Change-Id: Icac461a361dde969f023e7aa11f0605a97a3c009 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-01-19 05:20:37 +08:00
#else
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI) = 0;
#endif
}
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
#else /* _ASMLANGUAGE */
apic : Refactor some macros into a header Moving few macros into a header file. Change-Id: I975e19ba518bd6184038d6c1715224be7190b3ad Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-05-07 11:56:24 +08:00
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
#if CONFIG_EOI_FORWARDING_BUG
x86: implement direct interrupts Change-Id: Icac461a361dde969f023e7aa11f0605a97a3c009 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-01-19 05:20:37 +08:00
.macro __irq_controller_eoi_macro
all: Update reserved function names Update reserved function names starting with one underscore, replacing them as follows: '_k_' with 'z_' '_K_' with 'Z_' '_handler_' with 'z_handl_' '_Cstart' with 'z_cstart' '_Swap' with 'z_swap' This renaming is done on both global and those static function names in kernel/include and include/. Other static function names in kernel/ are renamed by removing the leading underscore. Other function names not starting with any prefix listed above are renamed starting with a 'z_' or 'Z_' prefix. Function names starting with two or three leading underscores are not automatcally renamed since these names will collide with the variants with two or three leading underscores. Various generator scripts have also been updated as well as perf, linker and usb files. These are drivers/serial/uart_handlers.c include/linker/kobject-text.ld kernel/include/syscall_handler.h scripts/gen_kobject_list.py scripts/gen_syscall_header.py Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2019-03-09 05:19:05 +08:00
call z_lakemont_eoi
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
.endm
#else
x86: implement direct interrupts Change-Id: Icac461a361dde969f023e7aa11f0605a97a3c009 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-01-19 05:20:37 +08:00
.macro __irq_controller_eoi_macro
jailhouse: add support for x2APIC mode for all LOAPIC accesses Besides the fact that we did not have that for the current supported boards, that makes sense for this new, virtualized mode, that is meant to be run on top of full-fledged x86 64 CPUs. By having xAPIC mode access only, Jailhouse has to intercept those MMIO reads and writes, in order to examine what they do and arbitrate if it's safe or not (e.g. not all values are accepted to ICR register). This means that we can't run away from having a VM-exit event for each and every access to APIC memory region and this impacts the latency the guest OS observes over bare metal a lot. When in x2APIC mode, Jailhouse does not require VM-exits for MSR accesses other that writes to the ICR register, so the latency the guest observes is reduced to almost zero. Here are some outputs of the the command line $ sudo ./tools/jailhouse cell stats tiny-demo on a Jailhouse's root cell console, for one of the Zephyr demos using LOAPIC timers, left for a couple of seconds: Statistics for tiny-demo cell (x2APIC root, x2APIC inmate) COUNTER SUM PER SEC vmexits_total 7 0 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_msr 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xapic 0 0 vmexits_xsetbv 0 0 Statistics for tiny-demo cell (xAPIC root, xAPIC inmate) COUNTER SUM PER SEC vmexits_total 4087 40 vmexits_xapic 4080 40 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_msr 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xsetbv 0 0 Statistics for tiny-demo cell (xAPIC root, x2APIC inmate) COUNTER SUM PER SEC vmexits_total 4087 40 vmexits_msr 4080 40 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xapic 0 0 vmexits_xsetbv 0 0 See that under x2APIC mode on both Jailhouse/root-cell and guest, the interruptions from the hypervisor are minimal. That is not the case when Jailhouse is on xAPIC mode, though. Note also that, as a plus, x2APIC accesses on the guest will map to xAPIC MMIO on the hypervisor just fine. Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
2017-10-12 05:17:12 +08:00
#ifdef CONFIG_JAILHOUSE_X2APIC
all: Update reserved function names Update reserved function names starting with one underscore, replacing them as follows: '_k_' with 'z_' '_K_' with 'Z_' '_handler_' with 'z_handl_' '_Cstart' with 'z_cstart' '_Swap' with 'z_swap' This renaming is done on both global and those static function names in kernel/include and include/. Other static function names in kernel/ are renamed by removing the leading underscore. Other function names not starting with any prefix listed above are renamed starting with a 'z_' or 'Z_' prefix. Function names starting with two or three leading underscores are not automatcally renamed since these names will collide with the variants with two or three leading underscores. Various generator scripts have also been updated as well as perf, linker and usb files. These are drivers/serial/uart_handlers.c include/linker/kobject-text.ld kernel/include/syscall_handler.h scripts/gen_kobject_list.py scripts/gen_syscall_header.py Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2019-03-09 05:19:05 +08:00
call z_jailhouse_eoi
jailhouse: add support for x2APIC mode for all LOAPIC accesses Besides the fact that we did not have that for the current supported boards, that makes sense for this new, virtualized mode, that is meant to be run on top of full-fledged x86 64 CPUs. By having xAPIC mode access only, Jailhouse has to intercept those MMIO reads and writes, in order to examine what they do and arbitrate if it's safe or not (e.g. not all values are accepted to ICR register). This means that we can't run away from having a VM-exit event for each and every access to APIC memory region and this impacts the latency the guest OS observes over bare metal a lot. When in x2APIC mode, Jailhouse does not require VM-exits for MSR accesses other that writes to the ICR register, so the latency the guest observes is reduced to almost zero. Here are some outputs of the the command line $ sudo ./tools/jailhouse cell stats tiny-demo on a Jailhouse's root cell console, for one of the Zephyr demos using LOAPIC timers, left for a couple of seconds: Statistics for tiny-demo cell (x2APIC root, x2APIC inmate) COUNTER SUM PER SEC vmexits_total 7 0 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_msr 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xapic 0 0 vmexits_xsetbv 0 0 Statistics for tiny-demo cell (xAPIC root, xAPIC inmate) COUNTER SUM PER SEC vmexits_total 4087 40 vmexits_xapic 4080 40 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_msr 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xsetbv 0 0 Statistics for tiny-demo cell (xAPIC root, x2APIC inmate) COUNTER SUM PER SEC vmexits_total 4087 40 vmexits_msr 4080 40 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xapic 0 0 vmexits_xsetbv 0 0 See that under x2APIC mode on both Jailhouse/root-cell and guest, the interruptions from the hypervisor are minimal. That is not the case when Jailhouse is on xAPIC mode, though. Note also that, as a plus, x2APIC accesses on the guest will map to xAPIC MMIO on the hypervisor just fine. Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
2017-10-12 05:17:12 +08:00
#else
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
xorl %eax, %eax /* zeroes eax */
loapic_eoi_reg = (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI)
movl %eax, loapic_eoi_reg /* tell LOAPIC the IRQ is handled */
jailhouse: add support for x2APIC mode for all LOAPIC accesses Besides the fact that we did not have that for the current supported boards, that makes sense for this new, virtualized mode, that is meant to be run on top of full-fledged x86 64 CPUs. By having xAPIC mode access only, Jailhouse has to intercept those MMIO reads and writes, in order to examine what they do and arbitrate if it's safe or not (e.g. not all values are accepted to ICR register). This means that we can't run away from having a VM-exit event for each and every access to APIC memory region and this impacts the latency the guest OS observes over bare metal a lot. When in x2APIC mode, Jailhouse does not require VM-exits for MSR accesses other that writes to the ICR register, so the latency the guest observes is reduced to almost zero. Here are some outputs of the the command line $ sudo ./tools/jailhouse cell stats tiny-demo on a Jailhouse's root cell console, for one of the Zephyr demos using LOAPIC timers, left for a couple of seconds: Statistics for tiny-demo cell (x2APIC root, x2APIC inmate) COUNTER SUM PER SEC vmexits_total 7 0 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_msr 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xapic 0 0 vmexits_xsetbv 0 0 Statistics for tiny-demo cell (xAPIC root, xAPIC inmate) COUNTER SUM PER SEC vmexits_total 4087 40 vmexits_xapic 4080 40 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_msr 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xsetbv 0 0 Statistics for tiny-demo cell (xAPIC root, x2APIC inmate) COUNTER SUM PER SEC vmexits_total 4087 40 vmexits_msr 4080 40 vmexits_management 3 0 vmexits_cr 2 0 vmexits_cpuid 1 0 vmexits_exception 0 0 vmexits_hypercall 0 0 vmexits_mmio 0 0 vmexits_pio 0 0 vmexits_xapic 0 0 vmexits_xsetbv 0 0 See that under x2APIC mode on both Jailhouse/root-cell and guest, the interruptions from the hypervisor are minimal. That is not the case when Jailhouse is on xAPIC mode, though. Note also that, as a plus, x2APIC accesses on the guest will map to xAPIC MMIO on the hypervisor just fine. Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
2017-10-12 05:17:12 +08:00
#endif
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
.endm
kconfig: fixed typo in CONFIG_EOI_FORMWARDING_BUG Change-Id: Ie142cb90525d1de92fada4e16a4a5d33d7a57206 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-10 21:52:25 +08:00
#endif /* CONFIG_EOI_FORWARDING_BUG */
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
#endif /* _ASMLANGUAGE */
apic : Refactor some macros into a header Moving few macros into a header file. Change-Id: I975e19ba518bd6184038d6c1715224be7190b3ad Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-05-07 11:56:24 +08:00
headers: Fix headers across the project Any word started with underscore followed by and uppercase letter or a second underscore is a reserved word according with C99. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-15 01:43:44 +08:00
#endif /* ZEPHYR_INCLUDE_DRIVERS_SYSAPIC_H_ */