zephyr/arch/riscv32/Kconfig

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arch: added support for the riscv32 architecture RISC-V is an open-source instruction set architecture. Added support for the 32bit version of RISC-V to Zephyr. 1) exceptions/interrupts/faults are handled at the architecture level via the __irq_wrapper handler. Context saving/restoring of registers can be handled at both architecture and SOC levels. If SOC-specific registers need to be saved, SOC level needs to provide __soc_save_context and __soc_restore_context functions that shall be accounted by the architecture level, when corresponding config variable RISCV_SOC_CONTEXT_SAVE is set. 2) As RISC-V architecture does not provide a clear ISA specification about interrupt handling, each RISC-V SOC handles it in its own way. Hence, at the architecture level, the __irq_wrapper handler expects the following functions to be provided by the SOC level: __soc_is_irq: to check if the exception is the result of an interrupt or not. __soc_handle_irq: handle pending IRQ at SOC level (ex: clear pending IRQ in SOC-specific IRQ register) 3) Thread/task scheduling, as well as IRQ offloading are handled via the RISC-V system call ("ecall"), which is also handled via the __irq_wrapper handler. The _Swap asm function just calls "ecall" to generate an exception. 4) As there is no conventional way of handling CPU power save in RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle functions just unlock interrupts and return to the caller, without issuing any CPU power saving instruction. Nonetheless, to allow SOC-level to implement proper CPU power save, nano_cpu_idle and nano_cpu_atomic_idle functions are defined as __weak at the architecture level. Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 07:24:30 +08:00
#
# Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
choice
prompt "RISCV32 configuration selection"
depends on RISCV32
source "arch/riscv32/soc/*/Kconfig.soc"
endchoice
menu "RISCV32 Options"
depends on RISCV32
config ARCH
string
default "riscv32"
config ARCH_DEFCONFIG
string
default "arch/riscv32/defconfig"
menu "RISCV32 Processor Options"
config INCLUDE_RESET_VECTOR
bool "Include Reset vector"
default n
help
Include the reset vector stub that inits CPU and then jumps to __start
config IRQ_OFFLOAD
bool "Enable IRQ offload"
default n
help
Enable irq_offload() API which allows functions to be synchronously
run in interrupt context. Mainly useful for test cases.
config RISCV_SOC_CONTEXT_SAVE
bool "Enable SOC-based context saving in IRQ handler"
default n
help
Enable SOC-based context saving, for SOCS which require saving of
extra registers when entering an interrupt/exception
config RISCV_SOC_INTERRUPT_INIT
bool "Enable SOC-based interrupt initialization"
default n
help
Enable SOC-based interrupt initialization
(call soc_interrupt_init, within _IntLibInit when enabled)
config RISCV_GENERIC_TOOLCHAIN
bool "Compile using generic riscv32 toolchain"
default y
help
Compile using generic riscv32 toolchain.
Allow SOCs that have custom extended riscv ISA to still
compile with generic riscv32 toolchain.
config RISCV_HAS_CPU_IDLE
bool "Does SOC has CPU IDLE instruction"
default n
help
Does SOC has CPU IDLE instruction
endmenu
source "arch/riscv32/soc/*/Kconfig"
endmenu