34 lines
918 B
ReStructuredText
34 lines
918 B
ReStructuredText
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.. _litex-vexriscv:
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LiteX VexRiscv
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##############
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Overview
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********
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LiteX is a Migen-based System on Chip, supporting various softcore CPUs,
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including VexRiscv. The LiteX SoC with VexRiscv CPU can be deployed on e.g.
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Digilent ARTY board. More information can be found on:
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`LiteX's website <https://github.com/enjoy-digital/litex>`_ and
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`VexRiscv's website <https://github.com/SpinalHDL/VexRiscv>`_.
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Programming and debugging
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*************************
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Building
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========
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Applications for the ``litex_vexriscv`` board configuration can be built as usual
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(see :ref:`build_an_application`).
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In order to build the application for ``litex_vexriscv``, set the ``BOARD`` variable
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to ``litex_vexriscv``.
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Booting
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=======
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You can boot from serial port using `flterm: <https://github.com/timvideos/flterm>`_, e.g.:
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.. code-block:: bash
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flterm --port /dev/ttyUSB0 --kernel <path_to_zephyr.bin> --kernel-adr 0x40000000
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