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zephyr/drivers/interrupt_controller/Makefile

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x86: Change SHUTOFF_PIC to PIC_DISABLE Make config variable name match the function. The PIC is never turned on in the zephyr code so there is nothing to shut off. Change-Id: I1627e5a35cc37ef7959f36758c1e1aec03e22782 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-09-10 02:25:04 +08:00
obj-${CONFIG_PIC_DISABLE} = i8259.o
x86/bsp: move local apic driver to drivers/interrupt_controller Change-Id: I69350493c3b94d754f89fb37eaebe50a8076384b Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-06 00:11:24 +08:00
x86: add Quark D2000 Interrupt Controller (MVIC) This module is based on the standard Local APIC and IO APIC source modules. This modules combines these modules into one source module that exports the same APIs defined by the Local APIC and IO APIC header modules. These routine have been adapted for the Quark D2000 Interrupt Controller which has a cutdown implementation of the Local APIC & IO APIC register sets. Change-Id: Ic80aa78918483663d76054ebadefa08d8a3f188a Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-07-31 18:57:00 +08:00
obj-$(CONFIG_MVIC) += mvic.o
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
obj-$(CONFIG_LOAPIC) += loapic_intr.o system_apic.o
x86/bsp: move io apic driver to drivers/interrupt_controller Change-Id: I00f400e0405f526dd17cf22c703fab4a4968fce0 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-06 01:48:18 +08:00
obj-$(CONFIG_IOAPIC) += ioapic_intr.o
loapic: handle spurious interrupts A special situation may occur when a processor raises its task priority to be greater than or equal to the level of the interrupt for which the processor INTR signal is currently being asserted. If at the time the INTA cycle is issued, the interrupt that was to be dispensed has become masked (programmed by software), the local APIC will deliver a spurious-interrupt vector. Dispensing the spurious-interrupt vector does not affect the ISR, so the handler for this vector should return without an EOI. Change-Id: I4cf4744bd6efd68b72e2c380269de4181dc80bd9 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2015-12-10 06:53:41 +08:00
obj-$(CONFIG_LOAPIC_SPURIOUS_VECTOR) += loapic_spurious.o
x86/bsp: move local apic driver to drivers/interrupt_controller Change-Id: I69350493c3b94d754f89fb37eaebe50a8076384b Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-06 00:11:24 +08:00
arc: move interrupt controller to drivers/ Change-Id: I731c99062f4b5d2d4d1eb6a3c546ed5f3e494fa4 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-06-20 21:26:06 +08:00
obj-$(CONFIG_ARCV2_INTERRUPT_UNIT) += arcv2_irq_unit.o
interupt_controller/stm32_exti: driver for STM32 EXTI controller Introcuce a driver for External Interrupt/Event Controller (EXTI) found on STM32 MCUs. Change-Id: Ib206521fcc51b5dfaaf5dea9d436f8304f3a36be Origin: Original Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-14 23:29:46 +08:00
stm32: rename CONFIG_SOC_STM32 -> CONFIG_SOC_FAMILY_STM32 Use CONFIG_SOC_FAMILY for the top level SoC family. A family will have different SoCs or different SoC series with multiple SoCs. Adding the Family string to the config variable to avoid confusion between actual SoCs and families and to prevent name collisions. Change-Id: Ic99a2c1df7850dee3a45641027af82464dd6fadb Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-03 10:29:40 +08:00
obj-$(CONFIG_SOC_FAMILY_STM32) += exti_stm32.o
interrupt_controller: added support for the SiFive Freedom E310 PLIC driver The SiFive Freedom E310 Platform Level Interrupt Controller (PLIC) follows the riscv PLIC specification as defined in the riscv privilege architecture specification. It provides implementation for the riscv PLIC APIs as required by the riscv-privilege SOC Family for SOCs providing support for the RISCV_HAS_PLIC config. Change-Id: I95d02edb53deeccd91e490776e8e1dbfb82d235f Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:16:30 +08:00
obj-$(CONFIG_PLIC_FE310) += plic_fe310.o