2021-01-06 18:24:54 +08:00
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/*
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* Copyright (c) 2020 Hans Unzner
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/f4/stm32f4.dtsi>
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/ {
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soc {
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spi2: spi@40003800 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <36 5>;
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status = "disabled";
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label = "SPI_2";
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};
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spi5: spi@40015000 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015000 0x400>;
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interrupts = <85 5>;
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status = "disabled";
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label = "SPI_5";
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};
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2021-04-19 22:57:49 +08:00
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i2s1: i2s@40013000 {
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compatible = "st,stm32-i2s";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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interrupts = <35 5>;
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dmas = <&dma2 3 3 0x400 0x3
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&dma2 2 3 0x400 0x3>;
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dma-names = "tx", "rx";
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status = "disabled";
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label = "I2S_1";
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};
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2021-01-06 18:24:54 +08:00
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i2s2: i2s@40003800 {
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compatible = "st,stm32-i2s";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <36 5>;
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dmas = <&dma1 4 0 0x400 0x3
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&dma1 3 0 0x400 0x3>;
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dma-names = "tx", "rx";
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status = "disabled";
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label = "I2S_2";
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};
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i2s5: i2s@40015000 {
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compatible = "st,stm32-i2s";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
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interrupts = <85 5>;
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dmas = <&dma2 6 7 0x400 0x3
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&dma2 5 7 0x400 0x3>;
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dma-names = "tx", "rx";
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status = "disabled";
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label = "I2S_5";
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};
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timers6: timers@40001000 {
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
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interrupts = <54 0>;
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interrupt-names = "global";
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status = "disabled";
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label = "TIMERS_6";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_6";
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#pwm-cells = <3>;
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};
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};
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dac1: dac@40007400 {
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compatible = "st,stm32-dac";
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reg = <0x40007400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
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status = "disabled";
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label = "DAC_1";
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#io-channel-cells = <1>;
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};
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};
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};
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