OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/drivers/ieee802154/ieee802154_mcr20a.h

183 lines
6.8 KiB
C
Raw Normal View History

drivers: ieee802154: add MCR20A driver Add driver and configuration for the MCR20A 802.15.4 transceiver. Jira: ZEP-1429 Change-Id: I0b17b688220a47c2f0e5cde269064bbd0dec824a Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-09 23:54:28 +08:00
/*
* Copyright (c) 2017 PHYTEC Messtechnik GmbH
*
* Portions of this file are derived from ieee802154_cc2520.h that is
* Copyright (c) 2016 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __IEEE802154_MCR20A_H__
#define __IEEE802154_MCR20A_H__
linker: move all linker headers to include/linker Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-17 23:30:47 +08:00
#include <linker/sections.h>
drivers: ieee802154: add MCR20A driver Add driver and configuration for the MCR20A 802.15.4 transceiver. Jira: ZEP-1429 Change-Id: I0b17b688220a47c2f0e5cde269064bbd0dec824a Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-09 23:54:28 +08:00
#include <atomic.h>
#include <spi.h>
/* Runtime context structure
***************************
*/
struct mcr20a_context {
struct net_if *iface;
/**************************/
struct device *irq_gpio;
struct device *reset_gpio;
struct gpio_callback irqb_cb;
drivers/ieee802154: Switch MCR20A driver to new SPI API And adding support for GPIO CS as well. It looks like the driver could benefit from centralizing all SPI access into a unique function, the protocol does not seem too convoluted to do so, like CC2520 or CC1200. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-05 17:51:26 +08:00
struct device *spi;
struct spi_config spi_cfg;
#if defined(CONFIG_IEEE802154_MCR20A_GPIO_SPI_CS)
struct spi_cs_control cs_ctrl;
#endif
net: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. Jira: ZEP-2051 Change-Id: I4ec03eb2183d59ef86ea2c20d956e5d272656837 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 22:27:50 +08:00
u8_t mac_addr[8];
drivers: mcr20a: cleanup and refactor interrupt processing The interrupt processing of MCR20A was flawed and complicated. This patch simplifies the handling of interrupts and reduces the number of necessary SPI transfers. Minor fixes: - use mutex for the PHY access control - remove unnecessary mcr20a_mask_irqb calls - do not read RX_FRM_LEN twice - increase timeout for sequence synchronization semaphore if the log level greater than 1 - enable only the Sequence-end (SEQIRQ) interrupt - fix magic in NET_DEVICE_INIT - make the timeout values dependent on the log level Change-Id: Ib3f64a092ffba91c80ff6e1d5cec995ab9d40bfb Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-31 19:00:06 +08:00
struct k_mutex phy_mutex;
struct k_sem isr_sem;
drivers: ieee802154: add MCR20A driver Add driver and configuration for the MCR20A 802.15.4 transceiver. Jira: ZEP-1429 Change-Id: I0b17b688220a47c2f0e5cde269064bbd0dec824a Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-09 23:54:28 +08:00
/*********TX + CCA*********/
struct k_sem seq_sync;
atomic_t seq_retval;
/************RX************/
drivers: use K_THREAD_STACK_DEFINE macros Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-03 05:08:45 +08:00
K_THREAD_STACK_MEMBER(mcr20a_rx_stack,
CONFIG_IEEE802154_MCR20A_RX_STACK_SIZE);
drivers: ieee802154: use k_thread_create() Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-10 03:15:00 +08:00
struct k_thread mcr20a_rx_thread;
drivers: ieee802154: add MCR20A driver Add driver and configuration for the MCR20A 802.15.4 transceiver. Jira: ZEP-1429 Change-Id: I0b17b688220a47c2f0e5cde269064bbd0dec824a Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-09 23:54:28 +08:00
};
#include "ieee802154_mcr20a_regs.h"
drivers/ieee802154: Switch MCR20A driver to new SPI API And adding support for GPIO CS as well. It looks like the driver could benefit from centralizing all SPI access into a unique function, the protocol does not seem too convoluted to do so, like CC2520 or CC1200. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-05 17:51:26 +08:00
u8_t _mcr20a_read_reg(struct mcr20a_context *dev, bool dreg, u8_t addr);
bool _mcr20a_write_reg(struct mcr20a_context *dev, bool dreg, u8_t addr,
net: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. Jira: ZEP-2051 Change-Id: I4ec03eb2183d59ef86ea2c20d956e5d272656837 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 22:27:50 +08:00
u8_t value);
drivers/ieee802154: Switch MCR20A driver to new SPI API And adding support for GPIO CS as well. It looks like the driver could benefit from centralizing all SPI access into a unique function, the protocol does not seem too convoluted to do so, like CC2520 or CC1200. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-05 17:51:26 +08:00
bool _mcr20a_write_burst(struct mcr20a_context *dev, bool dreg, u16_t addr,
net: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. Jira: ZEP-2051 Change-Id: I4ec03eb2183d59ef86ea2c20d956e5d272656837 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 22:27:50 +08:00
u8_t *data_buf, u8_t len);
drivers/ieee802154: Switch MCR20A driver to new SPI API And adding support for GPIO CS as well. It looks like the driver could benefit from centralizing all SPI access into a unique function, the protocol does not seem too convoluted to do so, like CC2520 or CC1200. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-05 17:51:26 +08:00
bool _mcr20a_read_burst(struct mcr20a_context *dev, bool dreg, u16_t addr,
net: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. Jira: ZEP-2051 Change-Id: I4ec03eb2183d59ef86ea2c20d956e5d272656837 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 22:27:50 +08:00
u8_t *data_buf, u8_t len);
drivers: ieee802154: add MCR20A driver Add driver and configuration for the MCR20A 802.15.4 transceiver. Jira: ZEP-1429 Change-Id: I0b17b688220a47c2f0e5cde269064bbd0dec824a Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-09 23:54:28 +08:00
drivers/ieee802154: Switch MCR20A driver to new SPI API And adding support for GPIO CS as well. It looks like the driver could benefit from centralizing all SPI access into a unique function, the protocol does not seem too convoluted to do so, like CC2520 or CC1200. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-05 17:51:26 +08:00
#define DEFINE_REG_READ(__reg_name, __reg_addr, __dreg) \
static inline u8_t read_reg_##__reg_name(struct mcr20a_context *dev) \
{ \
return _mcr20a_read_reg(dev, __dreg, __reg_addr); \
drivers: ieee802154: add MCR20A driver Add driver and configuration for the MCR20A 802.15.4 transceiver. Jira: ZEP-1429 Change-Id: I0b17b688220a47c2f0e5cde269064bbd0dec824a Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-09 23:54:28 +08:00
}
drivers/ieee802154: Switch MCR20A driver to new SPI API And adding support for GPIO CS as well. It looks like the driver could benefit from centralizing all SPI access into a unique function, the protocol does not seem too convoluted to do so, like CC2520 or CC1200. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-05 17:51:26 +08:00
#define DEFINE_REG_WRITE(__reg_name, __reg_addr, __dreg) \
static inline bool write_reg_##__reg_name(struct mcr20a_context *dev, \
u8_t value) \
{ \
return _mcr20a_write_reg(dev, __dreg, __reg_addr, value); \
drivers: ieee802154: add MCR20A driver Add driver and configuration for the MCR20A 802.15.4 transceiver. Jira: ZEP-1429 Change-Id: I0b17b688220a47c2f0e5cde269064bbd0dec824a Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-09 23:54:28 +08:00
}
#define DEFINE_DREG_READ(__reg_name, __reg_addr) \
DEFINE_REG_READ(__reg_name, __reg_addr, true)
#define DEFINE_DREG_WRITE(__reg_name, __reg_addr) \
DEFINE_REG_WRITE(__reg_name, __reg_addr, true)
#define DEFINE_IREG_READ(__reg_name, __reg_addr) \
DEFINE_REG_READ(__reg_name, __reg_addr, false)
#define DEFINE_IREG_WRITE(__reg_name, __reg_addr) \
DEFINE_REG_WRITE(__reg_name, __reg_addr, false)
DEFINE_DREG_READ(irqsts1, MCR20A_IRQSTS1)
DEFINE_DREG_READ(irqsts2, MCR20A_IRQSTS2)
DEFINE_DREG_READ(irqsts3, MCR20A_IRQSTS3)
DEFINE_DREG_READ(phy_ctrl1, MCR20A_PHY_CTRL1)
DEFINE_DREG_READ(phy_ctrl2, MCR20A_PHY_CTRL2)
DEFINE_DREG_READ(phy_ctrl3, MCR20A_PHY_CTRL3)
DEFINE_DREG_READ(rx_frm_len, MCR20A_RX_FRM_LEN)
DEFINE_DREG_READ(phy_ctrl4, MCR20A_PHY_CTRL4)
DEFINE_DREG_READ(src_ctrl, MCR20A_SRC_CTRL)
DEFINE_DREG_READ(cca1_ed_fnl, MCR20A_CCA1_ED_FNL)
DEFINE_DREG_READ(pll_int0, MCR20A_PLL_INT0)
DEFINE_DREG_READ(pa_pwr, MCR20A_PA_PWR)
DEFINE_DREG_READ(seq_state, MCR20A_SEQ_STATE)
DEFINE_DREG_READ(lqi_value, MCR20A_LQI_VALUE)
DEFINE_DREG_READ(rssi_cca_cnt, MCR20A_RSSI_CCA_CNT)
DEFINE_DREG_READ(asm_ctrl1, MCR20A_ASM_CTRL1)
DEFINE_DREG_READ(asm_ctrl2, MCR20A_ASM_CTRL2)
DEFINE_DREG_READ(overwrite_ver, MCR20A_OVERWRITE_VER)
DEFINE_DREG_READ(clk_out_ctrl, MCR20A_CLK_OUT_CTRL)
DEFINE_DREG_READ(pwr_modes, MCR20A_PWR_MODES)
DEFINE_DREG_WRITE(irqsts1, MCR20A_IRQSTS1)
DEFINE_DREG_WRITE(irqsts2, MCR20A_IRQSTS2)
DEFINE_DREG_WRITE(irqsts3, MCR20A_IRQSTS3)
DEFINE_DREG_WRITE(phy_ctrl1, MCR20A_PHY_CTRL1)
DEFINE_DREG_WRITE(phy_ctrl2, MCR20A_PHY_CTRL2)
DEFINE_DREG_WRITE(phy_ctrl3, MCR20A_PHY_CTRL3)
DEFINE_DREG_WRITE(phy_ctrl4, MCR20A_PHY_CTRL4)
DEFINE_DREG_WRITE(src_ctrl, MCR20A_SRC_CTRL)
DEFINE_DREG_WRITE(pll_int0, MCR20A_PLL_INT0)
DEFINE_DREG_WRITE(pa_pwr, MCR20A_PA_PWR)
DEFINE_DREG_WRITE(asm_ctrl1, MCR20A_ASM_CTRL1)
DEFINE_DREG_WRITE(asm_ctrl2, MCR20A_ASM_CTRL2)
DEFINE_DREG_WRITE(overwrite_ver, MCR20A_OVERWRITE_VER)
DEFINE_DREG_WRITE(clk_out_ctrl, MCR20A_CLK_OUT_CTRL)
DEFINE_DREG_WRITE(pwr_modes, MCR20A_PWR_MODES)
DEFINE_IREG_READ(part_id, MCR20A_PART_ID)
DEFINE_IREG_READ(rx_frame_filter, MCR20A_RX_FRAME_FILTER)
DEFINE_IREG_READ(cca1_thresh, MCR20A_CCA1_THRESH)
DEFINE_IREG_READ(cca1_ed_offset_comp, MCR20A_CCA1_ED_OFFSET_COMP)
DEFINE_IREG_READ(lqi_offset_comp, MCR20A_LQI_OFFSET_COMP)
DEFINE_IREG_READ(cca_ctrl, MCR20A_CCA_CTRL)
DEFINE_IREG_READ(cca2_corr_peaks, MCR20A_CCA2_CORR_PEAKS)
DEFINE_IREG_READ(cca2_thresh, MCR20A_CCA2_THRESH)
DEFINE_IREG_READ(tmr_prescale, MCR20A_TMR_PRESCALE)
DEFINE_IREG_READ(rx_byte_count, MCR20A_RX_BYTE_COUNT)
DEFINE_IREG_READ(rx_wtr_mark, MCR20A_RX_WTR_MARK)
DEFINE_IREG_WRITE(part_id, MCR20A_PART_ID)
DEFINE_IREG_WRITE(rx_frame_filter, MCR20A_RX_FRAME_FILTER)
DEFINE_IREG_WRITE(cca1_thresh, MCR20A_CCA1_THRESH)
DEFINE_IREG_WRITE(cca1_ed_offset_comp, MCR20A_CCA1_ED_OFFSET_COMP)
DEFINE_IREG_WRITE(lqi_offset_comp, MCR20A_LQI_OFFSET_COMP)
DEFINE_IREG_WRITE(cca_ctrl, MCR20A_CCA_CTRL)
DEFINE_IREG_WRITE(cca2_corr_peaks, MCR20A_CCA2_CORR_PEAKS)
DEFINE_IREG_WRITE(cca2_thresh, MCR20A_CCA2_THRESH)
DEFINE_IREG_WRITE(tmr_prescale, MCR20A_TMR_PRESCALE)
DEFINE_IREG_WRITE(rx_byte_count, MCR20A_RX_BYTE_COUNT)
DEFINE_IREG_WRITE(rx_wtr_mark, MCR20A_RX_WTR_MARK)
#define DEFINE_BITS_SET(__reg_name, __reg_addr, __nibble) \
net: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. Jira: ZEP-2051 Change-Id: I4ec03eb2183d59ef86ea2c20d956e5d272656837 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 22:27:50 +08:00
static inline u8_t set_bits_##__reg_name(u8_t value) \
drivers: ieee802154: add MCR20A driver Add driver and configuration for the MCR20A 802.15.4 transceiver. Jira: ZEP-1429 Change-Id: I0b17b688220a47c2f0e5cde269064bbd0dec824a Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-09 23:54:28 +08:00
{ \
value = (value << __reg_addr##__nibble##_SHIFT) & \
__reg_addr##__nibble##_MASK; \
return value; \
}
DEFINE_BITS_SET(phy_ctrl1_xcvseq, MCR20A_PHY_CTRL1, _XCVSEQ)
DEFINE_BITS_SET(phy_ctrl4_ccatype, MCR20A_PHY_CTRL4, _CCATYPE)
DEFINE_BITS_SET(pll_int0_val, MCR20A_PLL_INT0, _VAL)
DEFINE_BITS_SET(pa_pwr_val, MCR20A_PA_PWR, _VAL)
DEFINE_BITS_SET(tmr_prescale, MCR20A_TMR_PRESCALE, _VAL)
drivers: mcr20a: minor fixes and correction of the copyright header Some patches have been lost during rebase before the initial commit, this path fixes it. - correct copyright in registers definition header file - fix undefined macro inside CLK_OUT configuration - use the return value of k_sem_take if there is a timeout Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-07-25 17:37:27 +08:00
DEFINE_BITS_SET(clk_out_div, MCR20A_CLK_OUT, _DIV)
drivers: ieee802154: add MCR20A driver Add driver and configuration for the MCR20A 802.15.4 transceiver. Jira: ZEP-1429 Change-Id: I0b17b688220a47c2f0e5cde269064bbd0dec824a Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-09 23:54:28 +08:00
drivers/ieee802154: Switch MCR20A driver to new SPI API And adding support for GPIO CS as well. It looks like the driver could benefit from centralizing all SPI access into a unique function, the protocol does not seem too convoluted to do so, like CC2520 or CC1200. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-05 17:51:26 +08:00
#define DEFINE_BURST_WRITE(__reg_addr, __addr, __sz, __dreg) \
static inline bool write_burst_##__reg_addr( \
struct mcr20a_context *dev, u8_t *buf) \
{ \
return _mcr20a_write_burst(dev, __dreg, __addr, buf, __sz); \
drivers: ieee802154: add MCR20A driver Add driver and configuration for the MCR20A 802.15.4 transceiver. Jira: ZEP-1429 Change-Id: I0b17b688220a47c2f0e5cde269064bbd0dec824a Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-09 23:54:28 +08:00
}
#define DEFINE_BURST_READ(__reg_addr, __addr, __sz, __dreg) \
drivers/ieee802154: Switch MCR20A driver to new SPI API And adding support for GPIO CS as well. It looks like the driver could benefit from centralizing all SPI access into a unique function, the protocol does not seem too convoluted to do so, like CC2520 or CC1200. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-05 17:51:26 +08:00
static inline bool read_burst_##__reg_addr(struct mcr20a_context *dev, \
u8_t *buf) \
drivers: ieee802154: add MCR20A driver Add driver and configuration for the MCR20A 802.15.4 transceiver. Jira: ZEP-1429 Change-Id: I0b17b688220a47c2f0e5cde269064bbd0dec824a Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-09 23:54:28 +08:00
{ \
drivers/ieee802154: Switch MCR20A driver to new SPI API And adding support for GPIO CS as well. It looks like the driver could benefit from centralizing all SPI access into a unique function, the protocol does not seem too convoluted to do so, like CC2520 or CC1200. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-05 17:51:26 +08:00
return _mcr20a_read_burst(dev, __dreg, __addr, buf, __sz); \
drivers: ieee802154: add MCR20A driver Add driver and configuration for the MCR20A 802.15.4 transceiver. Jira: ZEP-1429 Change-Id: I0b17b688220a47c2f0e5cde269064bbd0dec824a Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-09 23:54:28 +08:00
}
DEFINE_BURST_WRITE(t1cmp, MCR20A_T1CMP_LSB, 3, true)
DEFINE_BURST_WRITE(t2cmp, MCR20A_T2CMP_LSB, 3, true)
DEFINE_BURST_WRITE(t3cmp, MCR20A_T3CMP_LSB, 3, true)
DEFINE_BURST_WRITE(t4cmp, MCR20A_T4CMP_LSB, 3, true)
DEFINE_BURST_WRITE(t2primecmp, MCR20A_T2PRIMECMP_LSB, 2, true)
DEFINE_BURST_WRITE(pll_int0, MCR20A_PLL_INT0, 3, true)
drivers: mcr20a: cleanup and refactor interrupt processing The interrupt processing of MCR20A was flawed and complicated. This patch simplifies the handling of interrupts and reduces the number of necessary SPI transfers. Minor fixes: - use mutex for the PHY access control - remove unnecessary mcr20a_mask_irqb calls - do not read RX_FRM_LEN twice - increase timeout for sequence synchronization semaphore if the log level greater than 1 - enable only the Sequence-end (SEQIRQ) interrupt - fix magic in NET_DEVICE_INIT - make the timeout values dependent on the log level Change-Id: Ib3f64a092ffba91c80ff6e1d5cec995ab9d40bfb Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-31 19:00:06 +08:00
DEFINE_BURST_WRITE(irqsts1_irqsts3, MCR20A_IRQSTS1, 3, true)
DEFINE_BURST_WRITE(irqsts1_ctrl1, MCR20A_IRQSTS1, 4, true)
drivers: ieee802154: add MCR20A driver Add driver and configuration for the MCR20A 802.15.4 transceiver. Jira: ZEP-1429 Change-Id: I0b17b688220a47c2f0e5cde269064bbd0dec824a Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-01-09 23:54:28 +08:00
DEFINE_BURST_WRITE(pan_id, MCR20A_MACPANID0_LSB, 2, false)
DEFINE_BURST_WRITE(short_addr, MCR20A_MACSHORTADDRS0_LSB, 2, false)
DEFINE_BURST_WRITE(ext_addr, MCR20A_MACLONGADDRS0_0, 8, false)
DEFINE_BURST_READ(event_timer, MCR20A_EVENT_TIMER_LSB, 3, true)
DEFINE_BURST_READ(irqsts1_ctrl4, MCR20A_IRQSTS1, 8, true)
#endif /* __IEEE802154_MCR20A_H__ */