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zephyr/drivers/i2c/Makefile

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i2c: Sort Makefile in alphabetical order. Change-Id: Id0b39b95a7f378d728ddbe0b92518af054072252 Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-11-19 01:03:28 +08:00
obj-$(CONFIG_I2C_ATMEL_SAM3) += i2c_atmel_sam3.o
interrupts: new static IRQ API The interrupt API has been redesigned: - irq_connect() for dynamic interrupts renamed to irq_connect_dynamic(). It will be used in situations where the new static irq_connect() won't work, i.e. the value of arguments can't be computed at build time - a new API for static interrupts replaces irq_connect(). it is used exactly the same way as its dynamic counterpart. The old static irq macros will be removed - Separate stub assembly files are no longer needed as the stubs are now generated inline with irq_connect() ReST documentation updated for the changed API. Some detail about the IDT in ROM added, and an oblique reference to the internal-only _irq_handler_set() API removed; we don't talk about internal APIs in the official documentation. Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-01-08 16:46:14 +08:00
obj-$(CONFIG_I2C_DW) += i2c_dw.o
i2c: Sort Makefile in alphabetical order. Change-Id: Id0b39b95a7f378d728ddbe0b92518af054072252 Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-11-19 01:03:28 +08:00
obj-$(CONFIG_I2C_MCUX) += i2c_mcux.o
i2c/nrf5: Implement NRF5 I2C driver. Basic interrupt driven i2c driver for the NRf5 series. The NRf5 series hardware imposes a constraint that various peripherals cannot be used simultaneously. This driver does not implement mutual exclusion against SPI, or SPIs drivers (yet). Change-Id: I308d93bc486eef95db7b95c6b7c9beafc0d7e97f Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-11-24 04:27:11 +08:00
obj-$(CONFIG_I2C_NRF5) += i2c_nrf5.o
i2c: Introduce QMSI I2C driver This patch introduces the QMSI I2C driver which is simply a shim driver based on I2C driver provided by QMSI BSP. This initial version supports only I2C_0 controller in 'master' mode. Due to some issues with qm_i2c_master_irq_transfer API, the driver uses the polling APIs from QMSI. This means that the current thread doesn't sleep (i.e. is not scheduled out) while the I2C transfer is carried out. The qm_i2c_master_irq_transfer() issue is under investigation. Below follows the missing features which will be addressed by a new version of this patch or by upcoming patches. * Block the current thread until the I2C operation has actually completed. * Add support for multiple controllers. * Add support for slave mode. * Add support for suspend() and resume() APIs. In order to enable this driver, the following options should be set: CONFIG_QMSI_DRIVERS=y CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory" CONFIG_I2C=y CONFIG_I2C_QMSI=y Finally, due to the lack of proper support for Quark SE in QMSI 1.0.0, this driver requires QMSI version greater than 1.0.0. This driver has been tested only with Quark SE based boards. Change-Id: I369992c7b5fe37f7e0b45be7f19e667ad1fca9ac Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-01-12 21:56:02 +08:00
obj-$(CONFIG_I2C_QMSI) += i2c_qmsi.o
i2c: quark se: Add QMSI 1.1-based I2C shim driver Add I2C QMSI shim driver for sensor system based on QMSI 1.1 Origin: Original Change-Id: I9c8efe49e8e9b7a5f8496fa49beb68e409148be7 Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-15 08:07:35 +08:00
obj-$(CONFIG_I2C_QMSI_SS) += i2c_qmsi_ss.o
stm32lx: add i2c driver for the L series Add the I2C for the STM32Lx series Change-Id: Id1694aeb3606b4fa9772bfb7a9f60e48a7cc93a8 Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-09-14 23:13:04 +08:00
obj-$(CONFIG_I2C_STM32LX) += i2c_stm32lx.o