90 lines
5.0 KiB
C
90 lines
5.0 KiB
C
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/*
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* Copyright (c) 2016 Piotr Mienkowski
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/** @file
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* @brief Definitions for IEEE 802.3, Section 2 MII compatible PHY transceivers
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*/
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#ifndef _MII_H_
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#define _MII_H_
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/* MII management registers */
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#define MII_BMCR 0x0 /** Basic Mode Control Register */
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#define MII_BMSR 0x1 /** Basic Mode Status Register */
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#define MII_PHYID1R 0x2 /** PHY ID 1 Register */
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#define MII_PHYID2R 0x3 /** PHY ID 2 Register */
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#define MII_ANAR 0x4 /** Auto-Negotiation Advertisement Register */
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#define MII_ANLPAR 0x5 /** Auto-Negotiation Link Partner Ability Reg */
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#define MII_ANER 0x6 /** Auto-Negotiation Expansion Register */
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#define MII_ANNPTR 0x7 /** Auto-Negotiation Next Page Transmit Register */
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#define MII_ANLPRNPR 0x8 /** Auto-Negotiation Link Partner Received Next Page Reg */
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#define MII_MMD_ACR 0xd /** MMD Access Control Register */
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#define MII_MMD_AADR 0xe /** MMD Access Address Data Register */
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#define MII_ESTAT 0xf /** Extended Status Register */
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/* Basic Mode Control Register (BMCR) bit definitions */
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#define MII_BMCR_RESET (1 << 15) /** PHY reset */
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#define MII_BMCR_LOOPBACK (1 << 14) /** enable loopback mode */
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#define MII_BMCR_SPEED_LSB (1 << 13) /** 10=1000Mbps 01=100Mbps; 00=10Mbps */
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#define MII_BMCR_AUTONEG_ENABLE (1 << 12) /** Auto-Negotiation enable */
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#define MII_BMCR_POWER_DOWN (1 << 11) /** power down mode */
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#define MII_BMCR_ISOLATE (1 << 10) /** isolate electrically PHY from MII */
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#define MII_BMCR_AUTONEG_RESTART (1 << 9) /** restart auto-negotiation */
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#define MII_BMCR_DUPLEX_MODE (1 << 8) /** full duplex mode */
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#define MII_BMCR_SPEED_MSB (1 << 6) /** 10=1000Mbps 01=100Mbps; 00=10Mbps */
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#define MII_BMCR_SPEED_MASK (1 << 6 | 1 << 13) /** Link Speed Field */
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#define MII_BMCR_SPEED_10 (0 << 6 | 0 << 13) /** select speed 10 Mb/s */
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#define MII_BMCR_SPEED_100 (0 << 6 | 1 << 13) /** select speed 100 Mb/s */
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#define MII_BMCR_SPEED_1000 (1 << 6 | 0 << 13) /** select speed 1000 Mb/s */
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/* Basic Mode Status Register (BMSR) bit definitions */
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#define MII_BMSR_100BASE_T4 (1 << 15) /** 100BASE-T4 capable */
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#define MII_BMSR_100BASE_X_FULL (1 << 14) /** 100BASE-X full duplex capable */
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#define MII_BMSR_100BASE_X_HALF (1 << 13) /** 100BASE-X half duplex capable */
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#define MII_BMSR_10_FULL (1 << 12) /** 10 Mb/s full duplex capable */
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#define MII_BMSR_10_HALF (1 << 11) /** 10 Mb/s half duplex capable */
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#define MII_BMSR_100BASE_T2_FULL (1 << 10) /** 100BASE-T2 full duplex capable */
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#define MII_BMSR_100BASE_T2_HALF (1 << 9) /** 100BASE-T2 half duplex capable */
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#define MII_BMSR_EXTEND_STATUS (1 << 8) /** extend status information in reg 15 */
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#define MII_BMSR_MF_PREAMB_SUPPR (1 << 6) /** PHY accepts management frames with preamble suppressed */
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#define MII_BMSR_AUTONEG_COMPLETE (1 << 5) /** Auto-negotiation process completed */
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#define MII_BMSR_REMOTE_FAULT (1 << 4) /** remote fault detected */
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#define MII_BMSR_AUTONEG_ABILITY (1 << 3) /** PHY is able to perform Auto-Negotiation */
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#define MII_BMSR_LINK_STATUS (1 << 2) /** link is up */
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#define MII_BMSR_JABBER_DETECT (1 << 1) /** jabber condition detected */
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#define MII_BMSR_EXTEND_CAPAB (1 << 0) /** extended register capabilities */
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/* Auto-negotiation Advertisement Register (ANAR) bit definitions */
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/* Auto-negotiation Link Partner Ability Register (ANLPAR) bit definitions */
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#define MII_ADVERTISE_NEXT_PAGE (1 << 15) /** next page */
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#define MII_ADVERTISE_LPACK (1 << 14) /** link partner acknowledge response */
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#define MII_ADVERTISE_REMOTE_FAULT (1 << 13) /** remote fault */
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#define MII_ADVERTISE_ASYM_PAUSE (1 << 11) /** try for asymmetric pause */
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#define MII_ADVERTISE_PAUSE (1 << 10) /** try for pause */
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#define MII_ADVERTISE_100BASE_T4 (1 << 9) /** try for 100BASE-T4 support */
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#define MII_ADVERTISE_100_FULL (1 << 8) /** try for 100BASE-X full duplex support */
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#define MII_ADVERTISE_100_HALF (1 << 7) /** try for 100BASE-X support */
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#define MII_ADVERTISE_10_FULL (1 << 6) /** try for 10 Mb/s full duplex support */
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#define MII_ADVERTISE_10_HALF (1 << 5) /** try for 10 Mb/s half duplex support */
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#define MII_ADVERTISE_SEL_MASK (0x1F << 0) /** Selector Field */
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#define MII_ADVERTISE_SEL_IEEE_802_3 0x01
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#define MII_ADVERTISE_ALL (MII_ADVERTISE_10_HALF | MII_ADVERTISE_10_FULL |\
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MII_ADVERTISE_100_HALF | MII_ADVERTISE_100_FULL |\
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MII_ADVERTISE_SEL_IEEE_802_3)
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#endif /* _MII_H_ */
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