zephyr/arch/xtensa/soc/intel_s1000/dts.fixup

/* SoC level DTS fixup file */

#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR	NS16550_80800_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE	NS16550_80800_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME		NS16550_80800_LABEL
#define CONFIG_UART_NS16550_PORT_0_IRQ		(NS16550_80800_IRQ_0 << 16) | \
						(SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
						(INTEL_CAVS_INTC_78800_IRQ_0 << 0)

#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI	NS16550_80800_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ	NS16550_80800_CLOCK_FREQUENCY

#define L2_SRAM_BASE				CONFIG_SRAM_BASE_ADDRESS

#define L2_SRAM_SIZE				CONFIG_SRAM_SIZE * 1024

#define DW_ICTL_BASE_ADDR			SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS

#define CONFIG_I2C_0_BASE_ADDR			SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS

#define CONFIG_I2C_0_BITRATE			SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY

#define CONFIG_I2C_0_NAME			SNPS_DESIGNWARE_I2C_80400_LABEL

#define CONFIG_I2C_0_IRQ			(SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \
						(SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
						(INTEL_CAVS_INTC_78800_IRQ_0 << 0)

#define CONFIG_I2C_0_IRQ_FLAGS			SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE
/* End of SoC Level DTS fixup file */