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zephyr/dts/arm/st/stm32f3-pinctrl.dtsi

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dts: arm: stm32f3: Add pinctrl node and uart pin configurations Add needed uart pinctrl configuration in pinmux node. This is done thanks to <soc>-pinctrl.dtsi file matching <soc>.dtsi files Populate stm32 f3 based boards dts files with references to uart pinctrl nodes Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-25 17:03:31 +08:00
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <dt-bindings/pinctrl/stm32-pinctrl.h>
/ {
soc {
pinctrl: pin-controller {
usart1_pins_a: usart1@0 {
rx_tx {
rx = <STM32_PIN_PB6 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PB7 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
usart1_pins_b: usart1@1 {
rx_tx {
rx = <STM32_PIN_PA10 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PA9 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
usart1_pins_c: usart1@2 {
rx_tx {
rx = <STM32_PIN_PG10 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PB6 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
stm32f3_disco: Switch USART1(Console) to PC4/PC5 Default configuration for USART1 (Console output) on board stm32f3_disco was set on PA9/PA10, which matches Rev-A/B configuration. Though, on more recent configuration of the board (Rev-C onward). USART1 is mapped to PC4/PC5. This configuration has the benefit to support VCP, hence it is chosen to be set by default. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-09-07 19:55:08 +08:00
usart1_pins_d: usart1@3 {
rx_tx {
rx = <STM32_PIN_PC5 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PC4 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
dts: arm: stm32f3: Add pinctrl node and uart pin configurations Add needed uart pinctrl configuration in pinmux node. This is done thanks to <soc>-pinctrl.dtsi file matching <soc>.dtsi files Populate stm32 f3 based boards dts files with references to uart pinctrl nodes Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-25 17:03:31 +08:00
usart2_pins_a: usart2@0 {
rx_tx {
rx = <STM32_PIN_PA3 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PA2 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
usart2_pins_b: usart2@1 {
rx_tx {
rx = <STM32_PIN_PA15 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PA2 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
usart2_pins_c: usart2@2 {
rx_tx {
rx = <STM32_PIN_PD6 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PA2 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
usart2_pins_d: usart2@3 {
rx_tx {
rx = <STM32_PIN_PD6 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PD5 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
usart3_pins_a: usart3@0 {
rx_tx {
rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PB10 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
usart3_pins_b: usart3@1 {
rx_tx {
rx = <STM32_PIN_PD9 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PD8 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
};
};
};
};
};