2016-12-13 19:53:08 +08:00
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/*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2018-09-15 01:43:44 +08:00
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#ifndef ZEPHYR_DRIVERS_COUNTER_DUALTIMER_CMSDK_APB_H_
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#define ZEPHYR_DRIVERS_COUNTER_DUALTIMER_CMSDK_APB_H_
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2016-12-13 19:53:08 +08:00
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#include <counter.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct dualtimer_cmsdk_apb {
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/* Offset: 0x000 (R/W) Timer 1 Load */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer1load;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer1value;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0x008 (R/W) Timer 1 Control */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer1ctrl;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer1intclr;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer1ris;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer1mis;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0x018 (R/W) Background Load Register */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer1bgload;
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2016-12-13 19:53:08 +08:00
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/* Reserved */
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2017-04-21 23:03:20 +08:00
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volatile u32_t reserved0;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0x020 (R/W) Timer 2 Load */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer2load;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer2value;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0x028 (R/W) Timer 2 Control */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer2ctrl;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer2intclr;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer2ris;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer2mis;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0x038 (R/W) Background Load Register */
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2017-04-21 23:03:20 +08:00
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volatile u32_t timer2bgload;
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2016-12-13 19:53:08 +08:00
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/* Reserved */
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2017-04-21 23:03:20 +08:00
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volatile u32_t reserved1[945];
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2016-12-13 19:53:08 +08:00
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/* Offset: 0xF00 (R/W) Integration Test Control Register */
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2017-04-21 23:03:20 +08:00
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volatile u32_t itcr;
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2016-12-13 19:53:08 +08:00
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/* Offset: 0xF04 ( /W) Integration Test Output Set Register */
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2017-04-21 23:03:20 +08:00
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volatile u32_t itop;
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2016-12-13 19:53:08 +08:00
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};
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#define DUALTIMER_CTRL_EN (1 << 7)
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#define DUALTIMER_CTRL_MODE (1 << 6)
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#define DUALTIMER_CTRL_INTEN (1 << 5)
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#define DUALTIMER_CTRL_PRESCALE (3 << 2)
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#define DUALTIMER_CTRL_SIZE_32 (1 << 1)
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#define DUALTIMER_CTRL_ONESHOOT (1 << 0)
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#define DUALTIMER_INTCLR (1 << 0)
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#define DUALTIMER_RAWINTSTAT (1 << 0)
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#define DUALTIMER_MASKINTSTAT (1 << 0)
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#ifdef __cplusplus
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}
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#endif
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2018-09-15 01:43:44 +08:00
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#endif /* ZEPHYR_DRIVERS_COUNTER_DUALTIMER_CMSDK_APB_H_ */
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