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zephyr/boards/riscv/qemu_riscv32/qemu_riscv32_xip_defconfig

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board: riscv: add qemu_riscv32_xip board to test XIP mode Add a variant riscv build target that only is run for tests tagged with "xip". Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-03-08 00:42:17 +08:00
# SPDX-License-Identifier: Apache-2.0
CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM=y
CONFIG_SOC_RISCV_SIFIVE_FREEDOM=y
CONFIG_BOARD_QEMU_RISCV32_XIP=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_SIFIVE_PORT_0=y
CONFIG_UART_CONSOLE=y
boards: FE310-based boards: transition to pinctrl driver This commit makes the transition from the pinmux driver to the pinctrl driver. It also modifies UART, SPI and I2C drivers used in FE310-based boards to use the new pinctrl API. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-03-22 16:38:57 +08:00
CONFIG_PINCTRL=y
board: riscv: add qemu_riscv32_xip board to test XIP mode Add a variant riscv build target that only is run for tests tagged with "xip". Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-03-08 00:42:17 +08:00
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000
CONFIG_QEMU_ICOUNT_SHIFT=6
riscv: Rework and cleanup Kconfig This patch is doing several things: - Core ISA and extension Kconfig symbols have now a formalized name (CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*) - a new Kconfig.isa file was introduced with the full set of extensions currently supported by the v2.2 spec - a new Kconfig.core file was introduced to host all the RISCV cores (currently only E31) - ISA and extensions settings are moved to SoC configuration files Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-05-12 18:03:47 +08:00
CONFIG_RISCV_CORE_E31=y