zephyr/boards/riscv/qemu_riscv32/qemu_riscv32_xip.dts

/*
 * Copyright (c) 2021 Jim Shu
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;

#include <sifive/riscv32-fe310.dtsi>
#include "qemu_riscv32_xip-pinctrl.dtsi"

/ {
	model = "SiFive HiFive 1";
	compatible = "sifive,hifive1";

	chosen {
		zephyr,console = &uart0;
		zephyr,shell-uart = &uart0;
		zephyr,sram = &dtim;
		zephyr,flash = &flash0;
	};

};

&gpio0 {
	status = "okay";
};

&uart0 {
	status = "okay";
	current-speed = <115200>;
	pinctrl-0 = <&uart0_rx_default &uart0_tx_default>;
	pinctrl-names = "default";
};

&spi0 {
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x10014000 0x1000 0x20400000 0xc00000>;
	flash0: flash@0 {
		compatible = "issi,is25lp128", "jedec,spi-nor";
		size = <134217728>;
		jedec-id = [96 60 18];
		reg = <0>;
		// Dummy entry
		spi-max-frequency = <0>;
	};
};