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zephyr/boards/riscv/litex_vexriscv/litex_vexriscv_defconfig

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boards: riscv32: add LiteX VexRiscV board Add LiteX VexRiscV board platform definitions and default configurations. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2019-03-28 21:50:13 +08:00
#
# Copyright (c) 2019 Antmicro <www.antmicro.com>
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_SOC_RISCV32_LITEX_VEXRISCV=y
CONFIG_BOARD_LITEX_VEXRISCV=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
boards: litex_vexriscv: Enable LiteX GPIO driver Enable LiteX GPIO driver in litex_vexriscv board. Signed-off-by: Robert Winkler <rwinkler@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
2019-08-05 18:05:36 +08:00
CONFIG_GPIO=y
arch: xip: cleanup XIP Kconfig unify how XIP is configured across architectures. Use imply instead of setting defaults per architecture and imply XIP on riscv arch and remove XIP configuration from individual defconfig files to match other architectures. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-02 22:45:10 +08:00
CONFIG_XIP=n
boards: riscv: litex_vexriscv: enable clock control driver This enables the LiteX clock control driver for litex_vexriscv platform. Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-05-11 19:52:52 +08:00
CONFIG_CLOCK_CONTROL=y
CONFIG_HEAP_MEM_POOL_SIZE=4096