2017-01-14 07:50:29 +08:00
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/* GCC specific test inline assembler functions and macros */
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/*
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* Copyright (c) 2015, Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _TEST_ASM_INLINE_GCC_H
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#define _TEST_ASM_INLINE_GCC_H
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#if !defined(__GNUC__)
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#error test_asm_inline_gcc.h goes only with GCC
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#endif
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#if defined(CONFIG_X86)
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static inline void timestamp_serialize(void)
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{
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__asm__ __volatile__ (/* serialize */
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"xorl %%eax,%%eax;\n\t"
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"cpuid;\n\t"
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:
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:
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: "%eax", "%ebx", "%ecx", "%edx");
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}
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arch/x86_64: New architecture added
This patch adds a x86_64 architecture and qemu_x86_64 board to Zephyr.
Only the basic architecture support needed to run 64 bit code is
added; no drivers are added, though a low-level console exists and is
wired to printk().
The support is built on top of a "X86 underkernel" layer, which can be
built in isolation as a unit test on a Linux host.
Limitations:
+ Right now the SDK lacks an x86_64 toolchain. The build will fall
back to a host toolchain if it finds no cross compiler defined,
which is tested to work on gcc 8.2.1 right now.
+ No x87/SSE/AVX usage is allowed. This is a stronger limitation than
other architectures where the instructions work from one thread even
if the context switch code doesn't support it. We are passing
-no-sse to prevent gcc from automatically generating SSE
instructions for non-floating-point purposes, which has the side
effect of changing the ABI. Future work to handle the FPU registers
will need to be combined with an "application" ABI distinct from the
kernel one (or just to require USERSPACE).
+ Paging is enabled (it has to be in long mode), but is a 1:1 mapping
of all memory. No MMU/USERSPACE support yet.
+ We are building with -mno-red-zone for stack size reasons, but this
is a valuable optimization. Enabling it requires automatic stack
switching, which requires a TSS, which means it has to happen after
MMU support.
+ The OS runs in 64 bit mode, but for compatibility reasons is
compiled to the 32 bit "X32" ABI. So while the full 64 bit
registers and instruction set are available, C pointers are 32 bits
long and Zephyr is constrained to run in the bottom 4G of memory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-08-20 03:24:48 +08:00
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#elif defined(CONFIG_X86_64)
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static inline void timestamp_serialize(void)
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{
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__asm__ volatile("xorq %%rax,%%rax; cpuid"
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::: "rax", "rdx", "rbx", "rcx");
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}
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2017-01-14 07:50:29 +08:00
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#elif defined(CONFIG_CPU_CORTEX_M)
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#include <arch/arm/cortex_m/cmsis.h>
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static inline void timestamp_serialize(void)
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{
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/* isb is avaialble in all Cortex-M */
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__ISB();
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}
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#elif defined(CONFIG_CPU_ARCV2)
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#define timestamp_serialize()
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2017-11-24 18:14:14 +08:00
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#elif defined(CONFIG_ARCH_POSIX)
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#define timestamp_serialize()
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2018-07-23 16:32:45 +08:00
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#elif defined(CONFIG_XTENSA)
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#define timestamp_serialize()
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#elif defined(CONFIG_NIOS2)
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#define timestamp_serialize()
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#elif defined(CONFIG_RISCV32)
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#define timestamp_serialize()
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2017-01-14 07:50:29 +08:00
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#else
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#error implementation of timestamp_serialize() not provided for your CPU target
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#endif
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#endif /* _TEST_ASM_INLINE_GCC_H */
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