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zephyr/soc/riscv32/riscv-privilege/riscv32-qemu/Kconfig.defconfig.series

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riscv32: added the riscv-privilege SOC_FAMILY added the riscv-privilege SOC_FAMILY, under which all riscv SOCs supporting the riscv privilege architecture specifcation shall reside. These SOCs shall notably have a common base for handling IRQs. Moved riscv32-qemu under the riscv-privilege SOC_FAMILY Change-Id: I5372cb38e3eaed78886f22b212ab4f881ef30b3f Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:12:24 +08:00
if SOC_SERIES_RISCV32_QEMU
riscv32: added support for the riscv32-qemu soc Change-Id: I7cf71f7a99fed7c83ed761ead9295697929d767d Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 07:24:30 +08:00
riscv32: added the riscv-privilege SOC_FAMILY added the riscv-privilege SOC_FAMILY, under which all riscv SOCs supporting the riscv privilege architecture specifcation shall reside. These SOCs shall notably have a common base for handling IRQs. Moved riscv32-qemu under the riscv-privilege SOC_FAMILY Change-Id: I5372cb38e3eaed78886f22b212ab4f881ef30b3f Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:12:24 +08:00
config SOC_SERIES
riscv32: added support for the riscv32-qemu soc Change-Id: I7cf71f7a99fed7c83ed761ead9295697929d767d Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 07:24:30 +08:00
string
default "riscv32-qemu"
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 10000000
config RISCV_SOC_INTERRUPT_INIT
bool
default y
config INCLUDE_RESET_VECTOR
bool
default y
config NUM_IRQS
int
default 32
riscv32: added a generic linker script for the riscv32 platform Added a linker script that shall be common to most riscv SOCs. Linker script also accounts for execution in place in ROM, when CONFIG_XIP is set. Nonetheless, riscv32 SOCs (like pulpino) requiring a different system layout can still define their own linker script. Change-Id: I3ad670446d439772c29a8204e307ac79643dc650 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-02-01 09:25:26 +08:00
config RISCV_RAM_SIZE_MB
riscv32: added support for the riscv32-qemu soc Change-Id: I7cf71f7a99fed7c83ed761ead9295697929d767d Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 07:24:30 +08:00
int
default 32
riscv32: added the riscv-privilege SOC_FAMILY added the riscv-privilege SOC_FAMILY, under which all riscv SOCs supporting the riscv privilege architecture specifcation shall reside. These SOCs shall notably have a common base for handling IRQs. Moved riscv32-qemu under the riscv-privilege SOC_FAMILY Change-Id: I5372cb38e3eaed78886f22b212ab4f881ef30b3f Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:12:24 +08:00
endif # SOC_SERIES_RISCV32_QEMU