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zephyr/arch/arm/core/swap.c

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arch: arm: Change method of __swap processing This patch reworks the current ARM __swap() function into a C function. Due to some issues with using svc calls withing fault handlers, we needed to change the way we initiate a swap by removing the dependence on svc #0. Before __swap() is called, the system has already done an irq_lock(). Upon return from __swap(), the equivalent of an irq_lock() is done due to restoration of the key value from the irq_lock preceeding the call. For ARM V6M (M0/M0+), the pendsv bit is toggled and the irqs are enabled. There is no priority masking in v6m, so it's just a global enable. For ARM V7M, the priority mask has to be set to 0x0 to allow for the pendsv IRQ to be taken. This is done for both via a call to irq_unlock(0). After this unlock, a pendsv irq will be taken, either at the tail end of the current irq handling if we are in handler mode, or immediately due to the pendsv being asserted (no other outstanding irqs). The next thread will be scheduled. Upon return from the context switch to the original thread, the priority mask will already be correct due to the pendsv processing. Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-22 14:22:45 +08:00
/*
* Copyright (c) 2018 Linaro, Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <kernel.h>
#include <toolchain.h>
#include <kernel_structs.h>
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_start_of_swap(void);
#endif
extern const int _k_neg_eagain;
/**
*
* @brief Initiate a cooperative context switch
*
* The __swap() routine is invoked by various kernel services to effect
* a cooperative context context switch. Prior to invoking __swap(), the caller
* disables interrupts via irq_lock() and the return 'key' is passed as a
* parameter to __swap(). The 'key' actually represents the BASEPRI register
* prior to disabling interrupts via the BASEPRI mechanism.
*
* __swap() itself does not do much.
*
* It simply stores the intlock key (the BASEPRI value) parameter into
* current->basepri, and then triggers a PendSV exception, which does
* the heavy lifting of context switching.
* This is the only place we have to save BASEPRI since the other paths to
* __pendsv all come from handling an interrupt, which means we know the
* interrupts were not locked: in that case the BASEPRI value is 0.
*
* Given that __swap() is called to effect a cooperative context switch,
* only the caller-saved integer registers need to be saved in the thread of the
* outgoing thread. This is all performed by the hardware, which stores it in
arch: arm: update function documentation for __svc Fixing the documentation for ARM core __svc function, which was outdated and present only for the ARMv7-M version. Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-02-11 18:07:58 +08:00
* its exception stack frame, created when handling the __pendsv exception.
arch: arm: Change method of __swap processing This patch reworks the current ARM __swap() function into a C function. Due to some issues with using svc calls withing fault handlers, we needed to change the way we initiate a swap by removing the dependence on svc #0. Before __swap() is called, the system has already done an irq_lock(). Upon return from __swap(), the equivalent of an irq_lock() is done due to restoration of the key value from the irq_lock preceeding the call. For ARM V6M (M0/M0+), the pendsv bit is toggled and the irqs are enabled. There is no priority masking in v6m, so it's just a global enable. For ARM V7M, the priority mask has to be set to 0x0 to allow for the pendsv IRQ to be taken. This is done for both via a call to irq_unlock(0). After this unlock, a pendsv irq will be taken, either at the tail end of the current irq handling if we are in handler mode, or immediately due to the pendsv being asserted (no other outstanding irqs). The next thread will be scheduled. Upon return from the context switch to the original thread, the priority mask will already be correct due to the pendsv processing. Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-22 14:22:45 +08:00
*
* On ARMv6-M, the intlock key is represented by the PRIMASK register,
* as BASEPRI is not available.
*
kernel: swap: Fix __swap signature __swap function was returning -EAGAIN in some case, though its return value was declared as unsigned int. This commit changes this function to return int since it can return a negative value and its return was already been propagate as int. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-12 09:33:37 +08:00
* @return -EAGAIN, or a return value set by a call to
all: Update reserved function names Update reserved function names starting with one underscore, replacing them as follows: '_k_' with 'z_' '_K_' with 'Z_' '_handler_' with 'z_handl_' '_Cstart' with 'z_cstart' '_Swap' with 'z_swap' This renaming is done on both global and those static function names in kernel/include and include/. Other static function names in kernel/ are renamed by removing the leading underscore. Other function names not starting with any prefix listed above are renamed starting with a 'z_' or 'Z_' prefix. Function names starting with two or three leading underscores are not automatcally renamed since these names will collide with the variants with two or three leading underscores. Various generator scripts have also been updated as well as perf, linker and usb files. These are drivers/serial/uart_handlers.c include/linker/kobject-text.ld kernel/include/syscall_handler.h scripts/gen_kobject_list.py scripts/gen_syscall_header.py Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2019-03-09 05:19:05 +08:00
* z_set_thread_return_value()
arch: arm: Change method of __swap processing This patch reworks the current ARM __swap() function into a C function. Due to some issues with using svc calls withing fault handlers, we needed to change the way we initiate a swap by removing the dependence on svc #0. Before __swap() is called, the system has already done an irq_lock(). Upon return from __swap(), the equivalent of an irq_lock() is done due to restoration of the key value from the irq_lock preceeding the call. For ARM V6M (M0/M0+), the pendsv bit is toggled and the irqs are enabled. There is no priority masking in v6m, so it's just a global enable. For ARM V7M, the priority mask has to be set to 0x0 to allow for the pendsv IRQ to be taken. This is done for both via a call to irq_unlock(0). After this unlock, a pendsv irq will be taken, either at the tail end of the current irq handling if we are in handler mode, or immediately due to the pendsv being asserted (no other outstanding irqs). The next thread will be scheduled. Upon return from the context switch to the original thread, the priority mask will already be correct due to the pendsv processing. Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-22 14:22:45 +08:00
*
*/
kernel: swap: Fix __swap signature __swap function was returning -EAGAIN in some case, though its return value was declared as unsigned int. This commit changes this function to return int since it can return a negative value and its return was already been propagate as int. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-12 09:33:37 +08:00
int __swap(int key)
arch: arm: Change method of __swap processing This patch reworks the current ARM __swap() function into a C function. Due to some issues with using svc calls withing fault handlers, we needed to change the way we initiate a swap by removing the dependence on svc #0. Before __swap() is called, the system has already done an irq_lock(). Upon return from __swap(), the equivalent of an irq_lock() is done due to restoration of the key value from the irq_lock preceeding the call. For ARM V6M (M0/M0+), the pendsv bit is toggled and the irqs are enabled. There is no priority masking in v6m, so it's just a global enable. For ARM V7M, the priority mask has to be set to 0x0 to allow for the pendsv IRQ to be taken. This is done for both via a call to irq_unlock(0). After this unlock, a pendsv irq will be taken, either at the tail end of the current irq handling if we are in handler mode, or immediately due to the pendsv being asserted (no other outstanding irqs). The next thread will be scheduled. Upon return from the context switch to the original thread, the priority mask will already be correct due to the pendsv processing. Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-22 14:22:45 +08:00
{
#ifdef CONFIG_EXECUTION_BENCHMARKING
read_timer_start_of_swap();
#endif
/* store off key and return value */
_current->arch.basepri = key;
_current->arch.swap_return_value = _k_neg_eagain;
arch: arm: Add Cortex-R support This adds initial Cortex-R support for interrupts and context switching. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2018-06-25 21:15:14 +08:00
#if defined(CONFIG_CPU_CORTEX_M)
arch: arm: Change method of __swap processing This patch reworks the current ARM __swap() function into a C function. Due to some issues with using svc calls withing fault handlers, we needed to change the way we initiate a swap by removing the dependence on svc #0. Before __swap() is called, the system has already done an irq_lock(). Upon return from __swap(), the equivalent of an irq_lock() is done due to restoration of the key value from the irq_lock preceeding the call. For ARM V6M (M0/M0+), the pendsv bit is toggled and the irqs are enabled. There is no priority masking in v6m, so it's just a global enable. For ARM V7M, the priority mask has to be set to 0x0 to allow for the pendsv IRQ to be taken. This is done for both via a call to irq_unlock(0). After this unlock, a pendsv irq will be taken, either at the tail end of the current irq handling if we are in handler mode, or immediately due to the pendsv being asserted (no other outstanding irqs). The next thread will be scheduled. Upon return from the context switch to the original thread, the priority mask will already be correct due to the pendsv processing. Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-22 14:22:45 +08:00
/* set pending bit to make sure we will take a PendSV exception */
SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
/* clear mask or enable all irqs to take a pendsv */
irq_unlock(0);
arch: arm: Add Cortex-R support This adds initial Cortex-R support for interrupts and context switching. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2018-06-25 21:15:14 +08:00
#elif defined(CONFIG_CPU_CORTEX_R)
cortex_r_svc();
irq_unlock(key);
#endif
arch: arm: Change method of __swap processing This patch reworks the current ARM __swap() function into a C function. Due to some issues with using svc calls withing fault handlers, we needed to change the way we initiate a swap by removing the dependence on svc #0. Before __swap() is called, the system has already done an irq_lock(). Upon return from __swap(), the equivalent of an irq_lock() is done due to restoration of the key value from the irq_lock preceeding the call. For ARM V6M (M0/M0+), the pendsv bit is toggled and the irqs are enabled. There is no priority masking in v6m, so it's just a global enable. For ARM V7M, the priority mask has to be set to 0x0 to allow for the pendsv IRQ to be taken. This is done for both via a call to irq_unlock(0). After this unlock, a pendsv irq will be taken, either at the tail end of the current irq handling if we are in handler mode, or immediately due to the pendsv being asserted (no other outstanding irqs). The next thread will be scheduled. Upon return from the context switch to the original thread, the priority mask will already be correct due to the pendsv processing. Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-22 14:22:45 +08:00
arch: arm: add explanatory comment in __swap() This commit adds an explanatory comment in ARM __swap() function, stressing when, exactly, context-switch is expected to occur, when we pend the PendSV exception. Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-03-06 21:42:32 +08:00
/* Context switch is performed here. Returning implies the
* thread has been context-switched-in again.
*/
arch: arm: Change method of __swap processing This patch reworks the current ARM __swap() function into a C function. Due to some issues with using svc calls withing fault handlers, we needed to change the way we initiate a swap by removing the dependence on svc #0. Before __swap() is called, the system has already done an irq_lock(). Upon return from __swap(), the equivalent of an irq_lock() is done due to restoration of the key value from the irq_lock preceeding the call. For ARM V6M (M0/M0+), the pendsv bit is toggled and the irqs are enabled. There is no priority masking in v6m, so it's just a global enable. For ARM V7M, the priority mask has to be set to 0x0 to allow for the pendsv IRQ to be taken. This is done for both via a call to irq_unlock(0). After this unlock, a pendsv irq will be taken, either at the tail end of the current irq handling if we are in handler mode, or immediately due to the pendsv being asserted (no other outstanding irqs). The next thread will be scheduled. Upon return from the context switch to the original thread, the priority mask will already be correct due to the pendsv processing. Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-22 14:22:45 +08:00
return _current->arch.swap_return_value;
}