2021-02-26 23:04:09 +08:00
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/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_flash_controller
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#define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash)
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#define FLASH_WRITE_BLK_SZ DT_PROP(SOC_NV_FLASH_NODE, write_block_size)
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#define FLASH_ERASE_BLK_SZ DT_PROP(SOC_NV_FLASH_NODE, erase_block_size)
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2021-10-08 23:44:01 +08:00
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/*
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* HAL includes go first to
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* avoid BIT macro redefinition
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*/
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2024-03-05 22:19:27 +08:00
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#include <esp_flash.h>
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#include <spi_flash_mmap.h>
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2021-10-08 23:44:01 +08:00
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#include <soc/spi_struct.h>
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2021-12-29 02:02:18 +08:00
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#include <esp_flash_encrypt.h>
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2024-03-05 22:19:27 +08:00
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#include <esp_flash_internal.h>
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2021-10-08 23:44:01 +08:00
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2022-05-06 16:25:46 +08:00
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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2021-02-26 23:04:09 +08:00
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#include <stddef.h>
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#include <string.h>
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#include <errno.h>
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2022-05-06 16:25:46 +08:00
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#include <zephyr/drivers/flash.h>
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2021-02-26 23:04:09 +08:00
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#include <soc.h>
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2022-05-06 16:25:46 +08:00
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#include <zephyr/logging/log.h>
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2021-02-26 23:04:09 +08:00
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LOG_MODULE_REGISTER(flash_esp32, CONFIG_FLASH_LOG_LEVEL);
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2023-05-20 03:07:29 +08:00
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#define FLASH_SEM_TIMEOUT (k_is_in_isr() ? K_NO_WAIT : K_FOREVER)
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2021-02-26 23:04:09 +08:00
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struct flash_esp32_dev_config {
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spi_dev_t *controller;
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};
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struct flash_esp32_dev_data {
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2023-05-09 17:10:05 +08:00
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#ifdef CONFIG_MULTITHREADING
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2021-02-26 23:04:09 +08:00
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struct k_sem sem;
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2023-05-09 17:10:05 +08:00
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#endif
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2021-02-26 23:04:09 +08:00
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};
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static const struct flash_parameters flash_esp32_parameters = {
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.write_block_size = FLASH_WRITE_BLK_SZ,
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.erase_value = 0xff,
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};
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2023-05-09 17:10:05 +08:00
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#ifdef CONFIG_MULTITHREADING
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2021-02-26 23:04:09 +08:00
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static inline void flash_esp32_sem_take(const struct device *dev)
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{
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2022-01-18 22:55:58 +08:00
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struct flash_esp32_dev_data *data = dev->data;
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2023-05-20 03:07:29 +08:00
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k_sem_take(&data->sem, FLASH_SEM_TIMEOUT);
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2021-02-26 23:04:09 +08:00
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}
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static inline void flash_esp32_sem_give(const struct device *dev)
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{
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2022-01-18 22:55:58 +08:00
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struct flash_esp32_dev_data *data = dev->data;
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k_sem_give(&data->sem);
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2021-02-26 23:04:09 +08:00
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}
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2023-05-09 17:10:05 +08:00
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#else
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#define flash_esp32_sem_take(dev) do {} while (0)
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#define flash_esp32_sem_give(dev) do {} while (0)
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#endif /* CONFIG_MULTITHREADING */
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2021-02-26 23:04:09 +08:00
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static int flash_esp32_read(const struct device *dev, off_t address, void *buffer, size_t length)
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{
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2021-12-29 02:02:18 +08:00
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int ret = 0;
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2021-02-26 23:04:09 +08:00
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flash_esp32_sem_take(dev);
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2021-12-29 02:02:18 +08:00
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if (!esp_flash_encryption_enabled()) {
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2024-03-05 22:19:27 +08:00
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ret = esp_flash_read(NULL, buffer, address, length);
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2021-12-29 02:02:18 +08:00
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} else {
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2024-03-05 22:19:27 +08:00
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ret = esp_flash_read_encrypted(NULL, address, buffer, length);
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2021-12-29 02:02:18 +08:00
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}
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2021-02-26 23:04:09 +08:00
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flash_esp32_sem_give(dev);
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2024-04-26 23:26:22 +08:00
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if (ret != 0) {
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LOG_ERR("esp_flash_read failed %d", ret);
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return -EIO;
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}
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return 0;
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2021-06-29 11:44:26 +08:00
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}
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static int flash_esp32_write(const struct device *dev,
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off_t address,
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const void *buffer,
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size_t length)
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{
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2021-12-29 02:02:18 +08:00
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int ret = 0;
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2021-06-29 11:44:26 +08:00
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flash_esp32_sem_take(dev);
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2021-12-29 02:02:18 +08:00
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if (!esp_flash_encryption_enabled()) {
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2024-03-05 22:19:27 +08:00
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ret = esp_flash_write(NULL, buffer, address, length);
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2021-12-29 02:02:18 +08:00
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} else {
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2024-03-05 22:19:27 +08:00
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ret = esp_flash_write_encrypted(NULL, address, buffer, length);
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2021-12-29 02:02:18 +08:00
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}
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2021-02-26 23:04:09 +08:00
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flash_esp32_sem_give(dev);
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2024-04-26 23:26:22 +08:00
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if (ret != 0) {
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LOG_ERR("esp_flash_write failed %d", ret);
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return -EIO;
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}
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return 0;
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2021-02-26 23:04:09 +08:00
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}
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static int flash_esp32_erase(const struct device *dev, off_t start, size_t len)
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{
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flash_esp32_sem_take(dev);
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2024-03-05 22:19:27 +08:00
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int ret = esp_flash_erase_region(NULL, start, len);
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2021-02-26 23:04:09 +08:00
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flash_esp32_sem_give(dev);
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2024-04-26 23:26:22 +08:00
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if (ret != 0) {
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LOG_ERR("esp_flash_erase_region failed %d", ret);
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return -EIO;
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}
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return 0;
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2021-02-26 23:04:09 +08:00
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}
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#if CONFIG_FLASH_PAGE_LAYOUT
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static const struct flash_pages_layout flash_esp32_pages_layout = {
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.pages_count = DT_REG_SIZE(SOC_NV_FLASH_NODE) / FLASH_ERASE_BLK_SZ,
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.pages_size = DT_PROP(SOC_NV_FLASH_NODE, erase_block_size),
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};
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void flash_esp32_page_layout(const struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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*layout = &flash_esp32_pages_layout;
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*layout_size = 1;
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}
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */
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static const struct flash_parameters *
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flash_esp32_get_parameters(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return &flash_esp32_parameters;
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}
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static int flash_esp32_init(const struct device *dev)
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{
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2024-03-05 22:19:27 +08:00
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uint32_t ret = 0;
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2021-02-26 23:04:09 +08:00
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2023-05-09 17:10:05 +08:00
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#ifdef CONFIG_MULTITHREADING
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2024-07-02 04:05:07 +08:00
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struct flash_esp32_dev_data *const dev_data = dev->data;
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2021-02-26 23:04:09 +08:00
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k_sem_init(&dev_data->sem, 1, 1);
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2023-05-09 17:10:05 +08:00
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#endif /* CONFIG_MULTITHREADING */
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2024-03-05 22:19:27 +08:00
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ret = esp_flash_init_default_chip();
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if (ret != 0) {
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LOG_ERR("esp_flash_init_default_chip failed %d", ret);
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return 0;
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}
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2021-02-26 23:04:09 +08:00
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return 0;
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}
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static const struct flash_driver_api flash_esp32_driver_api = {
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.read = flash_esp32_read,
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.write = flash_esp32_write,
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.erase = flash_esp32_erase,
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.get_parameters = flash_esp32_get_parameters,
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#ifdef CONFIG_FLASH_PAGE_LAYOUT
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.page_layout = flash_esp32_page_layout,
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#endif
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};
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static struct flash_esp32_dev_data flash_esp32_data;
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static const struct flash_esp32_dev_config flash_esp32_config = {
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.controller = (spi_dev_t *) DT_INST_REG_ADDR(0),
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};
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DEVICE_DT_INST_DEFINE(0, flash_esp32_init,
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2021-04-28 16:46:57 +08:00
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NULL,
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2021-02-26 23:04:09 +08:00
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&flash_esp32_data, &flash_esp32_config,
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2021-12-02 03:13:02 +08:00
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POST_KERNEL, CONFIG_FLASH_INIT_PRIORITY,
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2021-02-26 23:04:09 +08:00
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&flash_esp32_driver_api);
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