166 lines
8.2 KiB
C
166 lines
8.2 KiB
C
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/*
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* Copyright (c) 2021 IP-Logix Inc.
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* Arvin Farahmand <arvinf@ip-logix.com>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __DSA_KSZ8863_H__
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#define __DSA_KSZ8863_H__
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/* SPI commands */
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#define KSZ8863_SPI_CMD_WR (BIT(6))
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#define KSZ8863_SPI_CMD_RD (BIT(6) | BIT(5))
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/* PHY registers */
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#define KSZ8863_BMCR 0x00
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#define KSZ8863_BMSR 0x01
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#define KSZ8863_PHYID1 0x02
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#define KSZ8863_PHYID2 0x03
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#define KSZ8863_ANAR 0x04
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#define KSZ8863_ANLPAR 0x05
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#define KSZ8863_LINKMD 0x1D
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#define KSZ8863_PHYSCS 0x1F
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/* SWITCH registers */
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#define KSZ8863_CHIP_ID0 0x00
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#define KSZ8863_CHIP_ID1 0x01
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#define KSZ8863_GLOBAL_CTRL0 0x02
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#define KSZ8863_GLOBAL_CTRL1 0x03
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#define KSZ8863_GLOBAL_CTRL2 0x04
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#define KSZ8863_GLOBAL_CTRL3 0x05
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#define KSZ8863_GLOBAL_CTRL4 0x06
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#define KSZ8863_GLOBAL_CTRL5 0x07
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#define KSZ8863_GLOBAL_CTRL9 0x0B
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#define KSZ8863_GLOBAL_CTRL10 0x0C
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#define KSZ8863_GLOBAL_CTRL11 0x0D
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#define KSZ8863_GLOBAL_CTRL12 0x0E
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#define KSZ8863_GLOBAL_CTRL13 0x0F
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#define KSZ8863_PORT1_CTRL0 0x10
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#define KSZ8863_PORT1_CTRL1 0x11
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#define KSZ8863_PORT1_CTRL2 0x12
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#define KSZ8863_PORT1_CTRL3 0x13
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#define KSZ8863_PORT1_CTRL4 0x14
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#define KSZ8863_PORT1_CTRL5 0x15
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#define KSZ8863_PORT1_Q0_IG_LIMIT 0x16
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#define KSZ8863_PORT1_Q1_IG_LIMIT 0x17
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#define KSZ8863_PORT1_Q2_IG_LIMIT 0x18
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#define KSZ8863_PORT1_Q3_IG_LIMIT 0x19
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#define KSZ8863_PORT1_PHY_CTRL 0x1A
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#define KSZ8863_PORT1_LINKMD 0x1B
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#define KSZ8863_PORT1_CTRL12 0x1C
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#define KSZ8863_PORT1_CTRL13 0x1D
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#define KSZ8863_PORT1_STAT0 0x1E
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#define KSZ8863_PORT1_STAT1 0x1F
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#define KSZ8863_PORT2_CTRL0 0x20
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#define KSZ8863_PORT2_CTRL1 0x21
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#define KSZ8863_PORT2_CTRL2 0x22
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#define KSZ8863_PORT2_CTRL3 0x23
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#define KSZ8863_PORT2_CTRL4 0x24
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#define KSZ8863_PORT2_CTRL5 0x25
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#define KSZ8863_PORT2_Q0_IG_LIMIT 0x26
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#define KSZ8863_PORT2_Q1_IG_LIMIT 0x27
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#define KSZ8863_PORT2_Q2_IG_LIMIT 0x28
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#define KSZ8863_PORT2_Q3_IG_LIMIT 0x29
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#define KSZ8863_PORT2_PHY_CTRL 0x2A
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#define KSZ8863_PORT2_LINKMD 0x2B
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#define KSZ8863_PORT2_CTRL12 0x2C
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#define KSZ8863_PORT2_CTRL13 0x2D
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#define KSZ8863_PORT2_STAT0 0x2E
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#define KSZ8863_PORT2_STAT1 0x2F
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#define KSZ8863_PORT3_CTRL0 0x30
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#define KSZ8863_PORT3_CTRL1 0x31
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#define KSZ8863_PORT3_CTRL2 0x32
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#define KSZ8863_PORT3_CTRL3 0x33
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#define KSZ8863_PORT3_CTRL4 0x34
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#define KSZ8863_PORT3_CTRL5 0x35
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#define KSZ8863_PORT3_Q0_IG_LIMIT 0x36
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#define KSZ8863_PORT3_Q1_IG_LIMIT 0x37
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#define KSZ8863_PORT3_Q2_IG_LIMIT 0x38
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#define KSZ8863_PORT3_Q3_IG_LIMIT 0x39
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#define KSZ8863_PORT3_STAT1 0x3F
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#define KSZ8863_MAC_ADDR0 0x70
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#define KSZ8863_MAC_ADDR1 0x71
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#define KSZ8863_MAC_ADDR2 0x72
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#define KSZ8863_MAC_ADDR3 0x73
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#define KSZ8863_MAC_ADDR4 0x74
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#define KSZ8863_MAC_ADDR5 0x75
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#define KSZ8863_USER0 0x76
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#define KSZ8863_USER1 0x77
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#define KSZ8863_USER2 0x78
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#define KSZ8863_GLOBAL_CTRL1_TAIL_TAG_EN BIT(6)
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#define KSZ8863_GLOBAL_CTRL2_LEG_MAX_PKT_SIZ_CHK_ENA BIT(1)
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#define KSZ8863_CTRL2_PORTn(n) (0x12 + ((n) * 0x10))
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#define KSZ8863_CTRL2_TRANSMIT_EN BIT(2)
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#define KSZ8863_CTRL2_RECEIVE_EN BIT(1)
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#define KSZ8863_CTRL2_LEARNING_DIS BIT(0)
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#define KSZ8863_STAT2_PORTn(n) (0x1E + ((n) * 0x10))
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#define KSZ8863_STAT2_LINK_GOOD BIT(5)
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#define KSZ8863_CHIP_ID0_ID_DEFAULT 0x88
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#define KSZ8863_CHIP_ID1_ID_DEFAULT 0x31
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#define KSZ8863_REGISTER_67 0x43
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#define KSZ8863_SOFTWARE_RESET_SET BIT(4)
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#define KSZ8863_SOFTWARE_RESET_CLEAR 0
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enum {
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/* LAN ports for the ksz8863 switch */
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KSZ8863_PORT1 = 0,
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KSZ8863_PORT2,
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/* SWITCH <-> CPU port */
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KSZ8863_PORT3,
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};
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#define KSZ8863_REG_IND_CTRL_0 0x79
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#define KSZ8863_REG_IND_CTRL_1 0x7A
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#define KSZ8863_REG_IND_DATA_8 0x7B
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#define KSZ8863_REG_IND_DATA_7 0x7C
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#define KSZ8863_REG_IND_DATA_6 0x7D
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#define KSZ8863_REG_IND_DATA_5 0x7E
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#define KSZ8863_REG_IND_DATA_4 0x7F
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#define KSZ8863_REG_IND_DATA_3 0x80
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#define KSZ8863_REG_IND_DATA_2 0x81
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#define KSZ8863_REG_IND_DATA_1 0x82
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#define KSZ8863_REG_IND_DATA_0 0x83
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#define KSZ8863_STATIC_MAC_TABLE_VALID BIT(3)
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#define KSZ8863_STATIC_MAC_TABLE_OVRD BIT(4)
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#define KSZ8863_STATIC_MAC_TABLE_USE_FID BIT(5)
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#define KSZ8XXX_CHIP_ID0 KSZ8863_CHIP_ID0
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#define KSZ8XXX_CHIP_ID1 KSZ8863_CHIP_ID1
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#define KSZ8XXX_CHIP_ID0_ID_DEFAULT KSZ8863_CHIP_ID0_ID_DEFAULT
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#define KSZ8XXX_CHIP_ID1_ID_DEFAULT KSZ8863_CHIP_ID1_ID_DEFAULT
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#define KSZ8XXX_FIRST_PORT KSZ8863_PORT1
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#define KSZ8XXX_LAST_PORT KSZ8863_PORT3
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#define KSZ8XXX_CPU_PORT KSZ8863_PORT3
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#define KSZ8XXX_REG_IND_CTRL_0 KSZ8863_REG_IND_CTRL_0
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#define KSZ8XXX_REG_IND_CTRL_1 KSZ8863_REG_IND_CTRL_1
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#define KSZ8XXX_REG_IND_DATA_8 KSZ8863_REG_IND_DATA_8
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#define KSZ8XXX_REG_IND_DATA_7 KSZ8863_REG_IND_DATA_7
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#define KSZ8XXX_REG_IND_DATA_6 KSZ8863_REG_IND_DATA_6
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#define KSZ8XXX_REG_IND_DATA_5 KSZ8863_REG_IND_DATA_5
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#define KSZ8XXX_REG_IND_DATA_4 KSZ8863_REG_IND_DATA_4
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#define KSZ8XXX_REG_IND_DATA_3 KSZ8863_REG_IND_DATA_3
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#define KSZ8XXX_REG_IND_DATA_2 KSZ8863_REG_IND_DATA_2
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#define KSZ8XXX_REG_IND_DATA_1 KSZ8863_REG_IND_DATA_1
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#define KSZ8XXX_REG_IND_DATA_0 KSZ8863_REG_IND_DATA_0
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#define KSZ8XXX_STATIC_MAC_TABLE_VALID KSZ8863_STATIC_MAC_TABLE_VALID
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#define KSZ8XXX_STATIC_MAC_TABLE_OVRD KSZ8863_STATIC_MAC_TABLE_OVRD
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#define KSZ8XXX_STAT2_LINK_GOOD KSZ8863_STAT2_LINK_GOOD
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#define KSZ8XXX_RESET_REG KSZ8863_REGISTER_67
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#define KSZ8XXX_RESET_SET KSZ8863_SOFTWARE_RESET_SET
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#define KSZ8XXX_RESET_CLEAR KSZ8863_SOFTWARE_RESET_CLEAR
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#define KSZ8XXX_STAT2_PORTn KSZ8863_STAT2_PORTn
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#define KSZ8XXX_SPI_CMD_RD KSZ8863_SPI_CMD_RD
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#define KSZ8XXX_SPI_CMD_WR KSZ8863_SPI_CMD_WR
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#define KSZ8XXX_SOFT_RESET_DURATION 1000
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#define KSZ8XXX_HARD_RESET_WAIT 10000
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#endif /* __DSA_KSZ8863_H__ */
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