404 lines
11 KiB
C
404 lines
11 KiB
C
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/*
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* Copyright (c) 2023 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT snps_dw_timers
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#include <zephyr/device.h>
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#include <zephyr/drivers/counter.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/drivers/reset.h>
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#include <zephyr/drivers/clock_control.h>
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LOG_MODULE_REGISTER(dw_timer, CONFIG_COUNTER_LOG_LEVEL);
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static int counter_dw_timer_get_value(const struct device *timer_dev, uint32_t *ticks);
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/* DW APB timer register offsets */
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#define LOADCOUNT_OFST 0x0
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#define CURRENTVAL_OFST 0x4
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#define CONTROLREG_OFST 0x8
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#define EOI_OFST 0xc
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#define INTSTAT_OFST 0x10
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/* free running mode value */
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#define FREE_RUNNING_MODE_VAL 0xFFFFFFFFUL
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/* DW APB timer control flags */
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#define TIMER_CONTROL_ENABLE_BIT 0
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#define TIMER_MODE_BIT 1
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#define TIMER_INTR_MASK_BIT 2
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/* DW APB timer modes */
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#define USER_DEFINED_MODE 1
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#define FREE_RUNNING_MODE 0
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#define DEV_CFG(_dev) ((const struct counter_dw_timer_config *)(_dev)->config)
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#define DEV_DATA(_dev) ((struct counter_dw_timer_drv_data *const)(_dev)->data)
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/* Device Configuration */
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struct counter_dw_timer_config {
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struct counter_config_info info;
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DEVICE_MMIO_NAMED_ROM(timer_mmio);
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/* clock frequency of timer */
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uint32_t freq;
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(clocks)
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/* clock controller dev instance */
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const struct device *clk_dev;
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/* identifier for timer to get clock freq from clk manager */
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clock_control_subsys_t clkid;
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#endif
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets)
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/* reset controller device configuration*/
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const struct reset_dt_spec reset;
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#endif
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/* interrupt config function ptr */
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void (*irq_config)(void);
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};
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/* Driver data */
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struct counter_dw_timer_drv_data {
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/* mmio address mapping info */
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DEVICE_MMIO_NAMED_RAM(timer_mmio);
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(clocks)
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/* clock frequency of timer */
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uint32_t freq;
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#endif
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/* spin lock to protect user data */
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struct k_spinlock lock;
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/* top callback function */
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counter_top_callback_t top_cb;
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/* alarm callback function */
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counter_alarm_callback_t alarm_cb;
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/* private user data */
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void *prv_data;
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};
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static void counter_dw_timer_irq_handler(const struct device *timer_dev)
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{
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uint32_t ticks = 0;
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uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio);
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struct counter_dw_timer_drv_data *const data = DEV_DATA(timer_dev);
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k_spinlock_key_t key;
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counter_alarm_callback_t alarm_cb = data->alarm_cb;
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/* read EOI register to clear interrupt flag */
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sys_read32(reg_base + EOI_OFST);
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counter_dw_timer_get_value(timer_dev, &ticks);
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key = k_spin_lock(&data->lock);
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/* In case of alarm, mask interrupt and disable the callback. User
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* can configure the alarm in same context within callback function.
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*/
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if (data->alarm_cb) {
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sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);
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data->alarm_cb = NULL;
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alarm_cb(timer_dev, 0, ticks, data->prv_data);
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} else if (data->top_cb) {
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data->top_cb(timer_dev, data->prv_data);
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}
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k_spin_unlock(&data->lock, key);
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}
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static int counter_dw_timer_start(const struct device *dev)
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{
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uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, timer_mmio);
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/* disable timer before starting in free-running mode */
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sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);
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/* starting timer in free running mode */
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sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT);
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sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);
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sys_write32(FREE_RUNNING_MODE_VAL, reg_base + LOADCOUNT_OFST);
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/* enable timer */
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sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);
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return 0;
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}
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int counter_dw_timer_disable(const struct device *dev)
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{
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uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, timer_mmio);
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/* stop timer */
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sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);
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return 0;
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}
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static uint32_t counter_dw_timer_get_top_value(const struct device *timer_dev)
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{
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uint32_t top_val = 0;
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uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio);
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/* get the current top value from load count register */
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top_val = sys_read32(reg_base + LOADCOUNT_OFST);
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return top_val;
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}
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static int counter_dw_timer_get_value(const struct device *timer_dev, uint32_t *ticks)
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{
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uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio);
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/* current value of the current value register */
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*ticks = sys_read32(reg_base + CURRENTVAL_OFST);
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return 0;
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}
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static int counter_dw_timer_set_top_value(const struct device *timer_dev,
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const struct counter_top_cfg *top_cfg)
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{
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uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio);
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struct counter_dw_timer_drv_data *const data = DEV_DATA(timer_dev);
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k_spinlock_key_t key;
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if (top_cfg == NULL) {
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LOG_ERR("Invalid top value configuration");
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return -EINVAL;
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}
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/* top value cannot be updated without reset */
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if (top_cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
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LOG_ERR("Updating top value without reset is not supported");
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return -ENOTSUP;
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}
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key = k_spin_lock(&data->lock);
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/* top value cannot be updated if the alarm is active */
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if (data->alarm_cb) {
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k_spin_unlock(&data->lock, key);
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LOG_ERR("Top value cannot be updated, alarm is active!");
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return -EBUSY;
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}
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if (!top_cfg->callback) {
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/* mask an interrupt if callback is not passed */
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sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);
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} else {
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/* unmask interrupt if callback is passed */
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sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);
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}
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data->top_cb = top_cfg->callback;
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data->prv_data = top_cfg->user_data;
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/* top value can be loaded only when timer is stopped and re-enabled */
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sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);
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/* configuring timer in user-defined mode */
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sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT);
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/* set new top value */
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sys_write32(top_cfg->ticks, reg_base + LOADCOUNT_OFST);
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sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int counter_dw_timer_set_alarm(const struct device *timer_dev, uint8_t chan_id,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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ARG_UNUSED(chan_id);
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uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio);
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struct counter_dw_timer_drv_data *const data = DEV_DATA(timer_dev);
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k_spinlock_key_t key;
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if (alarm_cfg == NULL) {
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LOG_ERR("Invalid alarm configuration");
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return -EINVAL;
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}
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/* Alarm callback is mandatory */
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if (!alarm_cfg->callback) {
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LOG_ERR("Alarm callback function cannot be null");
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return -EINVAL;
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}
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/* absolute alarm is not supported as interrupts are triggered
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* only when the counter reaches 0(downcounter)
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*/
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if (alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) {
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LOG_ERR("Absolute alarm is not supported");
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return -ENOTSUP;
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}
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key = k_spin_lock(&data->lock);
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/* check if alarm is already active */
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if (data->alarm_cb != NULL) {
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LOG_ERR("Alarm is already active\n");
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k_spin_unlock(&data->lock, key);
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return -EBUSY;
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}
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data->alarm_cb = alarm_cfg->callback;
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data->prv_data = alarm_cfg->user_data;
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sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);
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/* start timer in user-defined mode */
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sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT);
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sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);
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sys_write32(alarm_cfg->ticks, reg_base + LOADCOUNT_OFST);
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sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int counter_dw_timer_cancel_alarm(const struct device *timer_dev, uint8_t chan_id)
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{
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ARG_UNUSED(chan_id);
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uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio);
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struct counter_dw_timer_drv_data *const data = DEV_DATA(timer_dev);
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k_spinlock_key_t key;
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key = k_spin_lock(&data->lock);
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sys_write32(0, reg_base + CONTROLREG_OFST);
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data->alarm_cb = NULL;
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data->prv_data = NULL;
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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uint32_t counter_dw_timer_get_freq(const struct device *timer_dev)
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{
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(clocks)
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struct counter_dw_timer_drv_data *const data = DEV_DATA(timer_dev);
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return data->freq;
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#else
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const struct counter_dw_timer_config *config = DEV_CFG(timer_dev);
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return config->freq;
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#endif
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}
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static const struct counter_driver_api dw_timer_driver_api = {
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.start = counter_dw_timer_start,
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.stop = counter_dw_timer_disable,
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.get_value = counter_dw_timer_get_value,
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.set_top_value = counter_dw_timer_set_top_value,
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.get_top_value = counter_dw_timer_get_top_value,
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.set_alarm = counter_dw_timer_set_alarm,
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.cancel_alarm = counter_dw_timer_cancel_alarm,
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.get_freq = counter_dw_timer_get_freq,
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};
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static int counter_dw_timer_init(const struct device *timer_dev)
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{
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DEVICE_MMIO_NAMED_MAP(timer_dev, timer_mmio, K_MEM_CACHE_NONE);
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const struct counter_dw_timer_config *timer_config = DEV_CFG(timer_dev);
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(clocks) || DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets)
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int ret;
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#endif
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/*
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* get clock rate from clock_frequency property if valid,
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* otherwise, get clock rate from clock manager
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*/
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(clocks)
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struct counter_dw_timer_drv_data *const data = DEV_DATA(timer_dev);
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if (!device_is_ready(timer_config->clk_dev)) {
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LOG_ERR("clock controller device not ready");
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return -ENODEV;
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}
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ret = clock_control_get_rate(timer_config->clk_dev,
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timer_config->clkid, &data->freq);
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if (ret != 0) {
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LOG_ERR("Unable to get clock rate: err:%d", ret);
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return ret;
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}
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#endif
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/* Reset timer only if reset controller driver is supported */
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#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets)
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if (timer_config->reset.dev != NULL) {
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if (!device_is_ready(timer_config->reset.dev)) {
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LOG_ERR("Reset controller device not ready");
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return -ENODEV;
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}
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ret = reset_line_toggle(timer_config->reset.dev, timer_config->reset.id);
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if (ret != 0) {
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LOG_ERR("Timer reset failed");
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return ret;
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}
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}
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#endif
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timer_config->irq_config();
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return 0;
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}
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#define DW_SNPS_TIMER_CLOCK_RATE_INIT(inst) \
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COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, clock_frequency), \
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( \
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.freq = DT_INST_PROP(inst, clock_frequency), \
|
||
|
|
), \
|
||
|
|
( \
|
||
|
|
.freq = 0, \
|
||
|
|
.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
|
||
|
|
.clkid = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(inst, clkid), \
|
||
|
|
) \
|
||
|
|
)
|
||
|
|
|
||
|
|
#define DW_SNPS_TIMER_SNPS_RESET_SPEC_INIT(inst) \
|
||
|
|
.reset = RESET_DT_SPEC_INST_GET(inst), \
|
||
|
|
|
||
|
|
#define CREATE_DW_TIMER_DEV(inst) \
|
||
|
|
static void counter_dw_timer_irq_config_##inst(void); \
|
||
|
|
static struct counter_dw_timer_drv_data timer_data_##inst; \
|
||
|
|
static const struct counter_dw_timer_config timer_config_##inst = { \
|
||
|
|
DEVICE_MMIO_NAMED_ROM_INIT(timer_mmio, DT_DRV_INST(inst)), \
|
||
|
|
DW_SNPS_TIMER_CLOCK_RATE_INIT(inst) \
|
||
|
|
.info = { \
|
||
|
|
.max_top_value = UINT32_MAX, \
|
||
|
|
.channels = 1, \
|
||
|
|
}, \
|
||
|
|
IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, resets), \
|
||
|
|
(DW_SNPS_TIMER_SNPS_RESET_SPEC_INIT(inst))) \
|
||
|
|
.irq_config = counter_dw_timer_irq_config_##inst, \
|
||
|
|
}; \
|
||
|
|
DEVICE_DT_INST_DEFINE(inst, \
|
||
|
|
counter_dw_timer_init, \
|
||
|
|
NULL, &timer_data_##inst, \
|
||
|
|
&timer_config_##inst, POST_KERNEL, \
|
||
|
|
CONFIG_COUNTER_INIT_PRIORITY, \
|
||
|
|
&dw_timer_driver_api); \
|
||
|
|
static void counter_dw_timer_irq_config_##inst(void) \
|
||
|
|
{ \
|
||
|
|
IRQ_CONNECT(DT_INST_IRQN(inst), \
|
||
|
|
DT_INST_IRQ(inst, priority), \
|
||
|
|
counter_dw_timer_irq_handler, \
|
||
|
|
DEVICE_DT_INST_GET(inst), 0); \
|
||
|
|
irq_enable(DT_INST_IRQN(inst)); \
|
||
|
|
}
|
||
|
|
|
||
|
|
DT_INST_FOREACH_STATUS_OKAY(CREATE_DW_TIMER_DEV);
|