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zephyr/drivers/cache/Kconfig

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cache: Introduce external cache controller system support The cache API currently shipped in Zephyr is assuming that the cache controller is always on-core thus managed at the arch level. This is not always the case because many SoCs rely on external cache controllers as a peripheral external to the core (for example PL310 cache controller and the L2Cxxx family). In some cases you also want a single driver to control a whole set of cache controllers. Rework the cache code introducing support for external cache controllers. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-04-28 16:38:27 +08:00
# Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0
menuconfig CACHE
drivers: kconfig: unify menuconfig title strings Unify the drivers/*/Kconfig menuconfig title strings to the format "<class> [(acronym)] [bus] drivers". Including both the full name of the driver class and an acronym makes menuconfig more user friendly as some of the acronyms are less well-known than others. It also improves Kconfig search, both via menuconfig and via the generated Kconfig documentation. Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2023-03-27 20:55:23 +08:00
bool "External cache controller drivers"
cache: kconfig: Reorder and fix entries The general Kconfig is at the moment a bit messy. Reorder and fix it. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-12-30 17:06:29 +08:00
default y if CACHE_MANAGEMENT
cache: Introduce external cache controller system support The cache API currently shipped in Zephyr is assuming that the cache controller is always on-core thus managed at the arch level. This is not always the case because many SoCs rely on external cache controllers as a peripheral external to the core (for example PL310 cache controller and the L2Cxxx family). In some cases you also want a single driver to control a whole set of cache controllers. Rework the cache code introducing support for external cache controllers. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-04-28 16:38:27 +08:00
help
Enable support for external cache controllers drivers
if CACHE
cache: kconfig: Reorder and fix entries The general Kconfig is at the moment a bit messy. Reorder and fix it. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-12-30 17:06:29 +08:00
config CACHE_HAS_DRIVER
bool
cache: Introduce external cache controller system support The cache API currently shipped in Zephyr is assuming that the cache controller is always on-core thus managed at the arch level. This is not always the case because many SoCs rely on external cache controllers as a peripheral external to the core (for example PL310 cache controller and the L2Cxxx family). In some cases you also want a single driver to control a whole set of cache controllers. Rework the cache code introducing support for external cache controllers. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-04-28 16:38:27 +08:00
module = CACHE
module-str = cache
source "subsys/logging/Kconfig.template.log_config"
cache: kconfig: Reorder and fix entries The general Kconfig is at the moment a bit messy. Reorder and fix it. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-12-30 17:06:29 +08:00
comment "Device Drivers"
cache: Add Aspeed AST10x0 external cache driver The CPU in Aspeed AST10x0 SOC is a ARM Cortex-M4 which doesn't internal cache memory. Aspeed implements an integrated system level cache to accelerate instruction and data memory accesses. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-05-13 15:20:31 +08:00
source "drivers/cache/Kconfig.aspeed"
drivers: cache: add Nordic cache driver Add Nordic driver for cache. Signed-off-by: Witold Lukasik <witold.lukasik@nordicsemi.no>
2023-12-11 22:01:50 +08:00
source "drivers/cache/Kconfig.nrf"
drivers: cache: add Andes cache driver Add cache driver for Andes cache. Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2024-01-22 16:32:21 +08:00
source "drivers/cache/Kconfig.andes"
cache: kconfig: Reorder and fix entries The general Kconfig is at the moment a bit messy. Reorder and fix it. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-12-30 17:06:29 +08:00
endif # CACHE