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zephyr/drivers/bbram/Kconfig

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nuvoton: battery-backed ram Add bindings and entry for the battery-backed ram in the nuvoton npcx. This commit is an upstream port of https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/cros_bbram/nuvoton,npcx-cros-bbram.yaml;l=1;drc=e9af813c36b7b411bf2a01cbc1b09d5fdec49b8a Along with a bit of cleaning up and an emulator. Signed-off-by: Yuval Peress <peress@chromium.org>
2021-01-25 15:51:17 +08:00
# Copyright (c) 2021 Google Inc
# SPDX-License-Identifier: Apache-2.0
menuconfig BBRAM
drivers: kconfig: unify menuconfig title strings Unify the drivers/*/Kconfig menuconfig title strings to the format "<class> [(acronym)] [bus] drivers". Including both the full name of the driver class and an acronym makes menuconfig more user friendly as some of the acronyms are less well-known than others. It also improves Kconfig search, both via menuconfig and via the generated Kconfig documentation. Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2023-03-27 20:55:23 +08:00
bool "Battery-backed RAM (BBRAM) drivers"
nuvoton: battery-backed ram Add bindings and entry for the battery-backed ram in the nuvoton npcx. This commit is an upstream port of https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/cros_bbram/nuvoton,npcx-cros-bbram.yaml;l=1;drc=e9af813c36b7b411bf2a01cbc1b09d5fdec49b8a Along with a bit of cleaning up and an emulator. Signed-off-by: Yuval Peress <peress@chromium.org>
2021-01-25 15:51:17 +08:00
help
Enable BBRAM (battery-backed RAM) driver configuration.
if BBRAM
module = BBRAM
module-str = bbram
source "subsys/logging/Kconfig.template.log_config"
drivers: bbram: Introduce BBRAM shell Add 'bbram' command which is very convenient tool for examining and modyfying BBRAM content. Examples: Write one byte: $ bbram write backup_regs 0x1 0xaa Write many bytes (starting from 0x13): $ bbram write backup_regs 0x13 0xa 0xb 0xc 0xd 0xe 0xf 0xaa 0xab 0xac Read whole BBRAM: $ bbram read backup_regs Read many bytes (4 bytes starting from address 0x14 in this case): $ bbram read backup_regs 0x14 4 Read one byte (from 0x14 address): $ bbram read backup_regs 0x14 Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-10-25 17:10:32 +08:00
config BBRAM_SHELL
bool "Battery-backed RAM shell"
depends on SHELL
help
Enable the BBRAM shell with read and write commands.
nuvoton: battery-backed ram Add bindings and entry for the battery-backed ram in the nuvoton npcx. This commit is an upstream port of https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/cros_bbram/nuvoton,npcx-cros-bbram.yaml;l=1;drc=e9af813c36b7b411bf2a01cbc1b09d5fdec49b8a Along with a bit of cleaning up and an emulator. Signed-off-by: Yuval Peress <peress@chromium.org>
2021-01-25 15:51:17 +08:00
config BBRAM_INIT_PRIORITY
int "Init priority"
drivers: bbram: Introduce STM32 BBRAM driver STM32 battery-backed RAM is organized in 4 byte registers. Number of registers can vary between models from 5 to 32 registers. Usually, the registers are part of RTC. On some variants they are part of tamper module. On STM32F1 the registers are in separate module. For now, only backup registers from RTC are supported. Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-10-24 22:37:21 +08:00
# In STM32, BBRAM is a part of RTC. In this case init priority must be
# lower than COUNTER_INIT_PRIORITY.
default 65 if BBRAM_STM32
drivers: bbram: Add Microchip MCP7940N driver Adds Microchip MCP7940N battery-backed RAM support. Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2023-02-24 20:12:43 +08:00
# MCP7940N is an I2C device, therefore the init priority must be
# greater than I2C_INIT_PRIORITY.
default 55 if BBRAM_MICROCHIP_MCP7940N
nuvoton: battery-backed ram Add bindings and entry for the battery-backed ram in the nuvoton npcx. This commit is an upstream port of https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/cros_bbram/nuvoton,npcx-cros-bbram.yaml;l=1;drc=e9af813c36b7b411bf2a01cbc1b09d5fdec49b8a Along with a bit of cleaning up and an emulator. Signed-off-by: Yuval Peress <peress@chromium.org>
2021-01-25 15:51:17 +08:00
default 10
help
BBRAM driver initialization priority
source "drivers/bbram/Kconfig.npcx"
drivers: bbram: Add it8xxx2 BBRAM driver implementation Note that the it8xxx2 does not support a status register so that functionality is omitted. This change also adds driver tests that build both the npcx and it8xxx2 drivers. Signed-off-by: Yuval Peress <peress@chromium.org>
2021-08-21 03:31:33 +08:00
source "drivers/bbram/Kconfig.it8xxx2"
nuvoton: battery-backed ram Add bindings and entry for the battery-backed ram in the nuvoton npcx. This commit is an upstream port of https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/cros_bbram/nuvoton,npcx-cros-bbram.yaml;l=1;drc=e9af813c36b7b411bf2a01cbc1b09d5fdec49b8a Along with a bit of cleaning up and an emulator. Signed-off-by: Yuval Peress <peress@chromium.org>
2021-01-25 15:51:17 +08:00
source "drivers/bbram/Kconfig.bbram_emul"
drivers: bbram: Add Microchip MCP7940N driver Adds Microchip MCP7940N battery-backed RAM support. Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2023-02-24 20:12:43 +08:00
source "drivers/bbram/Kconfig.microchip"
drivers: bbram: Add bbram driver for mec device Add bbram driver for Microchip mec device Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-02-04 03:14:26 +08:00
source "drivers/bbram/Kconfig.xec"
drivers: bbram: Introduce STM32 BBRAM driver STM32 battery-backed RAM is organized in 4 byte registers. Number of registers can vary between models from 5 to 32 registers. Usually, the registers are part of RTC. On some variants they are part of tamper module. On STM32F1 the registers are in separate module. For now, only backup registers from RTC are supported. Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-10-24 22:37:21 +08:00
source "drivers/bbram/Kconfig.stm32"
nuvoton: battery-backed ram Add bindings and entry for the battery-backed ram in the nuvoton npcx. This commit is an upstream port of https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/cros_bbram/nuvoton,npcx-cros-bbram.yaml;l=1;drc=e9af813c36b7b411bf2a01cbc1b09d5fdec49b8a Along with a bit of cleaning up and an emulator. Signed-off-by: Yuval Peress <peress@chromium.org>
2021-01-25 15:51:17 +08:00
endif # BBRAM