zephyr/boards/seeed/xiao_esp32c3/xiao_esp32c3_defconfig

# SPDX-License-Identifier: Apache-2.0

CONFIG_MAIN_STACK_SIZE=2048

CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
boards: riscv: add M5Stack STAMP-C3 Add M5Stack STAMP-C3 an ESP32-C3 based board. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com> 2022-12-18 23:15:51 +08:00			`# SPDX-License-Identifier: Apache-2.0`

			`CONFIG_MAIN_STACK_SIZE=2048`
soc: xtensa,riscv: esp32xx: refactor folder structure Refactor the ESP32 target SOCs together with all related boards. Most braking changes includes: - changing the CONFIG_SOC_ESP32* to refer to the actual soc line (esp32,esp32s2,esp32s3,esp32c3) - replacing CONFIG_SOC with the CONFIG_SOC_SERIES - creating CONFIG_SOC_FAMILY_ESP32 to embrace all the ESP32 across all used architectures - introducing CONFIG_SOC_PART_NUMBER_* to provide a SOC model config - introducing the 'common' folder to hide all commonly used configs and files. - updating west.yml to reflect previous changes in hal Signed-off-by: Marek Matej <marek.matej@espressif.com> 2023-07-21 00:24:09 +08:00
boards: riscv: add M5Stack STAMP-C3 Add M5Stack STAMP-C3 an ESP32-C3 based board. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com> 2022-12-18 23:15:51 +08:00			`CONFIG_CONSOLE=y`
			`CONFIG_SERIAL=y`
			`CONFIG_UART_CONSOLE=y`
			`CONFIG_GPIO=y`