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zephyr/boards/gaisler/generic_leon3/generic_leon3.dts

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boards: Add generic_leon3 for FPGA design This board configuration is compatible with - GRLIB GPL FPGA template designs - TSIM3 LEON3 eval Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-20 22:27:10 +08:00
/*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
dts: sparc: gaisler: Move SoC devicetree includes under a vendor dir Cleans up SoC devicetree include file locations to follow the convention of dts/<arch>/<vendor>/ Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2022-04-30 05:25:22 +08:00
#include <gaisler/leon3soc.dtsi>
boards: Add generic_leon3 for FPGA design This board configuration is compatible with - GRLIB GPL FPGA template designs - TSIM3 LEON3 eval Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-20 22:27:10 +08:00
/ {
dts/sparc/gaisler: add SoC and board compatible strings This commit adds compatible strings to Gaisler SoCs and boards in devicetree files. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2023-04-28 21:39:38 +08:00
model = "Generic LEON3 system";
compatible = "gaisler,generic-leon3";
boards: Add generic_leon3 for FPGA design This board configuration is compatible with - GRLIB GPL FPGA template designs - TSIM3 LEON3 eval Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-20 22:27:10 +08:00
chosen {
zephyr,console = &uart0;
board: set chosen zephyr,shell-uart in LEON boards DTS This associates the SHELL UART backend with the DTS uart0. It solves an issue with unresponsive shell. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-05-28 17:26:56 +08:00
zephyr,shell-uart = &uart0;
boards: Add generic_leon3 for FPGA design This board configuration is compatible with - GRLIB GPL FPGA template designs - TSIM3 LEON3 eval Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-20 22:27:10 +08:00
zephyr,sram = &ram0;
};
};
&ram0 {
reg = <0x40000000 0x00400000>;
};
&uart0 {
status = "okay";
};