73 lines
3.0 KiB
C
73 lines
3.0 KiB
C
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/*
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* Copyright (c) 2018 Intel Corporation.
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* Copyright (c) 2024 Meta.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/sw_isr_table.h>
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#include <zephyr/sys/util.h>
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/**
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* @file
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* @brief This file houses the deprecated legacy macros-generated multi-level interrupt lookup
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* table code, compiled when `CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` is enabled.
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*/
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/*
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* Insert code if the node_id is an interrupt controller
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*/
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#define Z_IF_DT_IS_INTC(node_id, code) \
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IF_ENABLED(DT_NODE_HAS_PROP(node_id, interrupt_controller), (code))
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/*
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* Expands to node_id if its IRQN is equal to `_irq`, nothing otherwise
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* This only works for `_irq` between 0 & 4095, see `IS_EQ`
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*/
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#define Z_IF_DT_INTC_IRQN_EQ(node_id, _irq) IF_ENABLED(IS_EQ(DT_IRQ(node_id, irq), _irq), (node_id))
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/*
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* Expands to node_id if it's an interrupt controller & its IRQN is `irq`, or nothing otherwise
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*/
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#define Z_DT_INTC_GET_IRQN(node_id, _irq) \
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Z_IF_DT_IS_INTC(node_id, Z_IF_DT_INTC_IRQN_EQ(node_id, _irq))
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/**
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* Loop through child of "/soc" and get root interrupt controllers with `_irq` as IRQN,
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* this assumes only one device has the IRQN
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* @param _irq irq number
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* @return node_id(s) that has the `_irq` number, or empty if none of them has the `_irq`
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*/
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#define INTC_DT_IRQN_GET(_irq) \
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DT_FOREACH_CHILD_STATUS_OKAY_VARGS(DT_PATH(soc), Z_DT_INTC_GET_IRQN, _irq)
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#define INIT_IRQ_PARENT_OFFSET_2ND(n, d, i, o) \
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IRQ_PARENT_ENTRY_DEFINE(intc_l2_##n, DEVICE_DT_GET_OR_NULL(d), i, o, 2)
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#define IRQ_INDEX_TO_OFFSET(i, base) (base + i * CONFIG_MAX_IRQ_PER_AGGREGATOR)
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#define CAT_2ND_LVL_LIST(i, base) \
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INIT_IRQ_PARENT_OFFSET_2ND(i, INTC_DT_IRQN_GET(CONFIG_2ND_LVL_INTR_0##i##_OFFSET), \
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CONFIG_2ND_LVL_INTR_0##i##_OFFSET, \
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IRQ_INDEX_TO_OFFSET(i, base))
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LISTIFY(CONFIG_NUM_2ND_LEVEL_AGGREGATORS, CAT_2ND_LVL_LIST, (;), CONFIG_2ND_LVL_ISR_TBL_OFFSET);
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#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
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BUILD_ASSERT((CONFIG_NUM_3RD_LEVEL_AGGREGATORS * CONFIG_MAX_IRQ_PER_AGGREGATOR) <=
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BIT(CONFIG_3RD_LEVEL_INTERRUPT_BITS),
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"L3 bits not enough to cover the number of L3 IRQs");
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#define INIT_IRQ_PARENT_OFFSET_3RD(n, d, i, o) \
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IRQ_PARENT_ENTRY_DEFINE(intc_l3_##n, DEVICE_DT_GET_OR_NULL(d), i, o, 3)
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#define CAT_3RD_LVL_LIST(i, base) \
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INIT_IRQ_PARENT_OFFSET_3RD(i, INTC_DT_IRQN_GET(CONFIG_3RD_LVL_INTR_0##i##_OFFSET), \
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CONFIG_3RD_LVL_INTR_0##i##_OFFSET, \
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IRQ_INDEX_TO_OFFSET(i, base))
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LISTIFY(CONFIG_NUM_3RD_LEVEL_AGGREGATORS, CAT_3RD_LVL_LIST, (;), CONFIG_3RD_LVL_ISR_TBL_OFFSET);
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#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
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