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zephyr/soc/riscv/riscv-privilege/miv/dts_fixup.h

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license: cleanup: add SPDX Apache-2.0 license identifier Update the files which contain no license information with the 'Apache-2.0' SPDX license identifier. Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of Zephyr, which is Apache version 2. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-06 21:08:09 +08:00
/* SPDX-License-Identifier: Apache-2.0 */
riscv: Add min dts support for miv SoC & m2gl025_miv board Add minimal DTS support for the m2gl025_miv. The dts just has the core, SoC, PLIC, and UART described. We still get memory related info from Kconfig. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-03 02:28:20 +08:00
soc/miv: Use DTS to generate PLIC addresses Describe the MMIO register regions for the PLIC in the DTS instead of hardcoded in soc.h. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-01 07:16:00 +08:00
/* PLIC */
#define DT_PLIC_MAX_PRIORITY \
dts: riscv: Add sifive,plic-1.0.0 binding and fix riscv,ndev values Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0 binding. The new binding adds a required riscv,ndev property, which gives the number of external interrupts supported. Use the new binding for microsemi-miv.dtsi (with a value of 31 for riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf) and riscv32-fe310.dtsi (which already assigns riscv,ndev). Also remove a spurious riscv,ndev assignment from riscv32-litex-vexriscv.dtsi. Also make edtlib and the old scripts/dts/ scripts replace '.' in compatible strings with '_' when generating identifiers. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-08-02 00:14:52 +08:00
DT_SIFIVE_PLIC_1_0_0_40000000_RISCV_MAX_PRIORITY
soc/miv: Use DTS to generate PLIC addresses Describe the MMIO register regions for the PLIC in the DTS instead of hardcoded in soc.h. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-01 07:16:00 +08:00
#define DT_PLIC_PRIO_BASE_ADDR \
dts: riscv: Add sifive,plic-1.0.0 binding and fix riscv,ndev values Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0 binding. The new binding adds a required riscv,ndev property, which gives the number of external interrupts supported. Use the new binding for microsemi-miv.dtsi (with a value of 31 for riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf) and riscv32-fe310.dtsi (which already assigns riscv,ndev). Also remove a spurious riscv,ndev assignment from riscv32-litex-vexriscv.dtsi. Also make edtlib and the old scripts/dts/ scripts replace '.' in compatible strings with '_' when generating identifiers. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-08-02 00:14:52 +08:00
DT_SIFIVE_PLIC_1_0_0_40000000_PRIO_BASE_ADDRESS
soc/miv: Use DTS to generate PLIC addresses Describe the MMIO register regions for the PLIC in the DTS instead of hardcoded in soc.h. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-01 07:16:00 +08:00
#define DT_PLIC_IRQ_EN_BASE_ADDR \
dts: riscv: Add sifive,plic-1.0.0 binding and fix riscv,ndev values Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0 binding. The new binding adds a required riscv,ndev property, which gives the number of external interrupts supported. Use the new binding for microsemi-miv.dtsi (with a value of 31 for riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf) and riscv32-fe310.dtsi (which already assigns riscv,ndev). Also remove a spurious riscv,ndev assignment from riscv32-litex-vexriscv.dtsi. Also make edtlib and the old scripts/dts/ scripts replace '.' in compatible strings with '_' when generating identifiers. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-08-02 00:14:52 +08:00
DT_SIFIVE_PLIC_1_0_0_40000000_IRQ_EN_BASE_ADDRESS
soc/miv: Use DTS to generate PLIC addresses Describe the MMIO register regions for the PLIC in the DTS instead of hardcoded in soc.h. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-01 07:16:00 +08:00
#define DT_PLIC_REG_BASE_ADDR \
dts: riscv: Add sifive,plic-1.0.0 binding and fix riscv,ndev values Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0 binding. The new binding adds a required riscv,ndev property, which gives the number of external interrupts supported. Use the new binding for microsemi-miv.dtsi (with a value of 31 for riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf) and riscv32-fe310.dtsi (which already assigns riscv,ndev). Also remove a spurious riscv,ndev assignment from riscv32-litex-vexriscv.dtsi. Also make edtlib and the old scripts/dts/ scripts replace '.' in compatible strings with '_' when generating identifiers. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-08-02 00:14:52 +08:00
DT_SIFIVE_PLIC_1_0_0_40000000_REG_BASE_ADDRESS
soc/miv: Use DTS to generate PLIC addresses Describe the MMIO register regions for the PLIC in the DTS instead of hardcoded in soc.h. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-01 07:16:00 +08:00
riscv: Add min dts support for miv SoC & m2gl025_miv board Add minimal DTS support for the m2gl025_miv. The dts just has the core, SoC, PLIC, and UART described. We still get memory related info from Kconfig. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-03 02:28:20 +08:00
/* UART 0 */
dts_fixups: Use DT_ prefix in all defined labels not related to Kconfig These changes were obtained by running a script created by Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following specification: 1. Read the contents of all dts_fixup.h files in Zephyr 2. Check the left-hand side of the #define macros (i.e. the X in #define X Y) 3. Check if that name is also the name of a Kconfig option 3.a If it is, then do nothing 3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it has neither of these two prefixes 4. Replace the use of the changed #define in the code itself (.c, .h, .ld) Additionally, some tweaks had to be added to this script to catch some of the macros used in the code in a parameterized form, e.g.: - CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS - CONFIG_UART_##idx##_TX_PIN - I2C_SBCON_##_num##_BASE_ADDR and to prevent adding DT_ prefix to the following symbols: - FLASH_START - FLASH_SIZE - SRAM_START - SRAM_SIZE - _ROM_ADDR - _ROM_SIZE - _RAM_ADDR - _RAM_SIZE which are surprisingly also defined in some dts_fixup.h files. Finally, some manual corrections had to be done as well: - name##_IRQ -> DT_##name##_IRQ in uart_stm32.c Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-11-13 22:15:23 +08:00
#define DT_MIV_UART_0_BASE_ADDR DT_MICROSEMI_COREUART_70001000_BASE_ADDRESS
#define DT_MIV_UART_0_CLOCK_FREQUENCY DT_MICROSEMI_COREUART_70001000_CLOCK_FREQUENCY
#define DT_MIV_UART_0_BAUD_RATE DT_MICROSEMI_COREUART_70001000_CURRENT_SPEED
#define DT_MIV_UART_0_NAME DT_MICROSEMI_COREUART_70001000_LABEL