2017-04-04 05:35:53 +08:00
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#include <arm/armv7-m.dtsi>
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2017-02-05 11:50:45 +08:00
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#include <inc/hw_ints.h>
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2017-04-19 05:18:50 +08:00
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#include <ti/mem.h>
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2017-02-05 11:50:45 +08:00
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2017-04-19 05:18:50 +08:00
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/* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC32XX SDK */
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2017-02-05 11:50:45 +08:00
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/* which are offset by 16: */
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#define EXP_UARTA0 (INT_UARTA0 - 16)
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#define EXP_UARTA1 (INT_UARTA1 - 16)
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/ {
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cpus {
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cpu@0 {
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compatible = "arm,cortex-m4";
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};
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};
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sram0: memory {
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compatible = "sram";
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2017-04-19 05:18:50 +08:00
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reg = <DT_SRAM_START DT_SRAM_SIZE>;
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2017-02-05 11:50:45 +08:00
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};
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flash0: serial-flash {
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compatible = "serial-flash";
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2017-04-19 05:18:50 +08:00
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reg = <0x0 DT_SFLASH_SIZE>;
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2017-02-05 11:50:45 +08:00
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};
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2017-04-19 05:43:44 +08:00
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flash1: flash {
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reg = <0x01000000 DT_FLASH_SIZE>;
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};
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2017-02-05 11:50:45 +08:00
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soc {
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2017-04-13 06:18:44 +08:00
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uart0: uart@4000C000 {
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2017-02-05 11:50:45 +08:00
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compatible = "ti,cc32xx-uart";
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2017-04-13 06:18:44 +08:00
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reg = <0x4000C000 0x4c>;
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2017-03-24 02:41:32 +08:00
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interrupts = <EXP_UARTA0 3>;
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2017-02-05 11:50:45 +08:00
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status = "disabled";
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};
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2017-04-13 06:18:44 +08:00
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uart1: uart@4000D000 {
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2017-02-05 11:50:45 +08:00
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compatible = "ti,cc32xx-uart";
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2017-04-13 06:18:44 +08:00
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reg = <0x4000D000 0x4c>;
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2017-03-24 02:41:32 +08:00
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interrupts = <EXP_UARTA1 3>;
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2017-02-05 11:50:45 +08:00
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status = "disabled";
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};
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};
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};
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&nvic {
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2017-03-28 01:13:40 +08:00
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arm,num-irq-priority-bits = <3>;
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2017-02-05 11:50:45 +08:00
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};
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