74 lines
3.1 KiB
C
74 lines
3.1 KiB
C
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/*
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* Copyright (c) 2021 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_FPGA_EOS_S3_H_
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#define ZEPHYR_DRIVERS_FPGA_EOS_S3_H_
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#include <eoss3_dev.h>
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struct PIF_struct {
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/* Fabric Configuration Control Register, offset: 0x000 */
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__IO uint32_t CFG_CTL;
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/* Maximum Bit Length Count, offset: 0x004 */
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__IO uint32_t MAX_BL_CNT;
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/* Maximum Word Length Count, offset: 0x008 */
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__IO uint32_t MAX_WL_CNT;
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uint32_t reserved[1020];
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/* Configuration Data, offset: 0xFFC */
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__IO uint32_t CFG_DATA;
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};
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#define PIF ((struct PIF_struct *)PIF_CTRL_BASE)
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#define FB_CFG_ENABLE ((uint32_t)(0x00000200))
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#define FB_CFG_DISABLE ((uint32_t)(0x00000000))
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#define CFG_CTL_APB_CFG_WR ((uint32_t)(0x00008000))
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#define CFG_CTL_APB_CFG_RD ((uint32_t)(0x00004000))
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#define CFG_CTL_APB_WL_DIN ((uint32_t)(0x00003C00))
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#define CFG_CTL_APB_PARTIAL_LOAD ((uint32_t)(0x00000200))
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#define CFG_CTL_APB_BL_SEL ((uint32_t)(0x00000100))
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#define CFG_CTL_APB_BLM_SEL ((uint32_t)(0x00000080))
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#define CFG_CTL_APB_BR_SEL ((uint32_t)(0x00000040))
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#define CFG_CTL_APB_BRM_SEL ((uint32_t)(0x00000020))
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#define CFG_CTL_APB_TL_SEL ((uint32_t)(0x00000010))
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#define CFG_CTL_APB_TLM_SEL ((uint32_t)(0x00000008))
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#define CFG_CTL_APB_TR_SEL ((uint32_t)(0x00000004))
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#define CFG_CTL_APB_TRM_SEL ((uint32_t)(0x00000002))
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#define CFG_CTL_APB_SEL_CFG ((uint32_t)(0x00000001))
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#define FB_ISOLATION_ENABLE ((uint32_t)(0x00000001))
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#define FB_ISOLATION_DISABLE ((uint32_t)(0x00000000))
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#define PMU_FFE_FB_PF_SW_PD_FB_PD ((uint32_t)(0x00000002))
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#define PMU_FB_PWR_MODE_CFG_FB_SD ((uint32_t)(0x00000002))
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#define PMU_FB_PWR_MODE_CFG_FB_DP ((uint32_t)(0x00000001))
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#define FPGA_INFO \
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"eos_s3 eFPGA features:\n" \
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"891 Logic Cells\n" \
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"8 FIFO Controllers\n" \
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"32 Configurable Interfaces\n" \
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"2x32x32(or 4x16x16) Multiplier\n" \
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"64Kbit SRAM\n"
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#define PAD_ENABLE \
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(PAD_E_4MA | PAD_P_PULLDOWN | PAD_OEN_NORMAL | PAD_SMT_DISABLE | PAD_REN_DISABLE | \
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PAD_SR_SLOW | PAD_CTRL_SEL_AO_REG)
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#define PAD_DISABLE \
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(PAD_SMT_DISABLE | PAD_REN_DISABLE | PAD_SR_SLOW | PAD_E_4MA | PAD_P_PULLDOWN | \
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PAD_OEN_NORMAL | PAD_CTRL_SEL_AO_REG)
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#define CFG_CTL_LOAD_ENABLE \
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(CFG_CTL_APB_CFG_WR | CFG_CTL_APB_WL_DIN | CFG_CTL_APB_BL_SEL | CFG_CTL_APB_BLM_SEL | \
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CFG_CTL_APB_BR_SEL | CFG_CTL_APB_BRM_SEL | CFG_CTL_APB_TL_SEL | CFG_CTL_APB_TLM_SEL | \
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CFG_CTL_APB_TR_SEL | CFG_CTL_APB_TRM_SEL | CFG_CTL_APB_SEL_CFG)
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#define CFG_CTL_LOAD_DISABLE 0
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#endif /* ZEPHYR_DRIVERS_FPGA_EOS_S3_H_ */
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