zephyr/soc/arm/nxp_imx/rt/linker.ld

/*
 * Copyright (c) 2014 Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arch/arm/cortex_m/scripts/linker.ld>
arch: Add imx7d m4 soc support The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual Cortex A7 core and Single Cortex M4 core. Zephyr was ported to run on the M4 core. In a later release, it will also communicate with the A7 core (running Linux) via RPmsg. The low level drivers come from NXP FreeRTOS BSP and are located at ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README The A7 core is responsible to load the M4 binary application into the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get the M4 out of reset. The A7 can perform these steps at bootloader level after the Linux system has booted. The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4: +---------------+-----------------+---------------------------+ \| Memory Name \| Start Address \| Size \| +===============+=================+===========================+ \| TCML \| 0x007F8000 \| 32KB \| +---------------+-----------------+---------------------------+ \| TCMU \| 0x20000000 \| 32KB \| +---------------+-----------------+---------------------------+ \| OCRAM_S \| 0x20180000 \| 32KB \| +---------------+-----------------+---------------------------+ \| OCRAM \| 0x00900000 \| 128KB \| +---------------+-----------------+---------------------------+ \| DDR \| 0x10000000 \| 256MB \| +---------------+-----------------+---------------------------+ Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com> 2018-03-16 21:59:33 +08:00			`/*`
			`* Copyright (c) 2014 Wind River Systems, Inc.`
			`*`
			`* SPDX-License-Identifier: Apache-2.0`
			`*/`

			`#include <arch/arm/cortex_m/scripts/linker.ld>`