43 lines
1.3 KiB
C
43 lines
1.3 KiB
C
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/*
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* Copyright (c) 2021, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/cpu.h>
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#include <arch/arm64/arm_mmu.h>
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static const struct arm_mmu_region mmu_regions[] = {
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/* System manager register that required by clock driver */
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MMU_REGION_FLAT_ENTRY("SYSTEM_MANAGER",
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DT_REG_ADDR(DT_NODELABEL(sysmgr)),
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DT_REG_SIZE(DT_NODELABEL(sysmgr)),
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MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
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MMU_REGION_FLAT_ENTRY("CLOCK",
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DT_REG_ADDR(DT_NODELABEL(clock)),
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DT_REG_SIZE(DT_NODELABEL(clock)),
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MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
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MMU_REGION_FLAT_ENTRY("UART0",
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DT_REG_ADDR(DT_NODELABEL(uart0)),
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DT_REG_SIZE(DT_NODELABEL(uart0)),
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MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
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MMU_REGION_FLAT_ENTRY("GIC",
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DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
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DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
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MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
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MMU_REGION_FLAT_ENTRY("GIC",
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DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
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DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
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MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
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};
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const struct arm_mmu_config mmu_config = {
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.num_regions = ARRAY_SIZE(mmu_regions),
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.mmu_regions = mmu_regions,
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};
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