63 lines
1.7 KiB
Plaintext
63 lines
1.7 KiB
Plaintext
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# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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# SPDX-License-Identifier: Apache-2.0
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# Infineon CAT1A devices
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# Family definitions
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config SOC_FAMILY_PSOC6
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select ARM
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select CPU_CORTEX_M4
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select CPU_HAS_ARM_MPU
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select DYNAMIC_INTERRUPTS
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select CPU_HAS_FPU
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select SOC_FAMILY_INFINEON_CAT1
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config SOC_FAMILY_PSOC6_LEGACY
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select ARM
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select HAS_CYPRESS_DRIVERS
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_HAS_ARM_MPU
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config SOC_FAMILY_PSOC6_LEGACY_M4
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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config SOC_FAMILY_PSOC6_LEGACY_M0
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_VTOR
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config SOC_PSOC6_M0_ENABLES_M4
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bool "Dual-core support [activate Cortex-M4]"
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depends on SOC_FAMILY_PSOC6_LEGACY_M0
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help
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Cortex-M0 CPU should boot Cortex-M4
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if SOC_FAMILY_PSOC6
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## PSoC™ 6 Cortex M0+ prebuilt images
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choice
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prompt "PSoC™ 6 Cortex M0+ prebuilt images"
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help
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Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSoC™ 6
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dual-core MCU. The image is responsible for booting the Cortex-M4 on the device.
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config SOC_PSOC6_CM0P_IMAGE_SLEEP
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bool "DeepSleep"
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help
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DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSoC™ 6 BLE
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dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4
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application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4
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linker script.
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endchoice
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config SOC_PSOC6_CM0P_IMAGE_ROM_SIZE
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hex
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default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP
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config SOC_PSOC6_CM0P_IMAGE_RAM_SIZE
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hex
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default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP
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endif # SOC_FAMILY_PSOC6
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