zephyr/soc/riscv/riscv-privilege/starfive_jh71xx/Kconfig.soc

# Copyright (c) 2021 Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
# SPDX-License-Identifier: Apache-2.0

choice
	prompt "Starfive JH7100 SoC"
	depends on SOC_SERIES_STARFIVE_JH71XX

config SOC_JH7100
	bool "Starfive JH7100"
	select ATOMIC_OPERATIONS_BUILTIN
	select INCLUDE_RESET_VECTOR

endchoice
boards: risc-v: add BeagleV Starlight JH7100 board support Adding support for beagleV Starlight board based on Starfive JH7100 SoC. It's a base support, no drivers other than uart has been tested. Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> 2021-05-18 08:57:18 +08:00			`# Copyright (c) 2021 Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>`
			`# SPDX-License-Identifier: Apache-2.0`

			`choice`
			`prompt "Starfive JH7100 SoC"`
			`depends on SOC_SERIES_STARFIVE_JH71XX`

			`config SOC_JH7100`
			`bool "Starfive JH7100"`
			`select ATOMIC_OPERATIONS_BUILTIN`
soc: riscv: priv: call __reset during boot Call __reset instead of directly calling __initialize from the common RISC-V privileged SoC vectors __start. This allows injection of SoC specific reset code just after setting up the machine trap vector. RISC-V privilege SoCs without the need for custom reset code can set CONFIG_INCLUDE_RESET_VECTOR=y to include a __reset stub which simply calls __initialize. Fixes: #38396 Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk> 2021-09-09 04:20:10 +08:00			`select INCLUDE_RESET_VECTOR`
boards: risc-v: add BeagleV Starlight JH7100 board support Adding support for beagleV Starlight board based on Starfive JH7100 SoC. It's a base support, no drivers other than uart has been tested. Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> 2021-05-18 08:57:18 +08:00
			`endchoice`