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zephyr/arch/common/isr_tables.c

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gen_isr_tables: New static interrupt build mechanism This is a new mechanism for generating interrupt tables which will be useful on many architectures. It replaces the old linker-based mechanism for creating these tables and has a couple advantages: 1) It is now possible to use enums as the IRQ line argument to IRQ_CONNECT(), which should ease CMSIS integration. 2) The vector table itself is now generated, which lets us place interrupts directly into the vector table without having to hard-code them. This is a feature we have long enjoyed on x86 and will enable 'direct' interrupts. 3) More code is common, requiring less arch-specific code to support. This patch introduces the common code for this mechanism. Follow-up patches will enable it on various arches. Issue: ZEP-1038, ZEP-1165 Change-Id: I9acd6e0de8b438fa9293f2e00563628f7510168a Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-09 09:16:29 +08:00
/*
* Copyright (c) 2017 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <toolchain.h>
linker: move all linker headers to include/linker Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-17 23:30:47 +08:00
#include <linker/sections.h>
gen_isr_tables: New static interrupt build mechanism This is a new mechanism for generating interrupt tables which will be useful on many architectures. It replaces the old linker-based mechanism for creating these tables and has a couple advantages: 1) It is now possible to use enums as the IRQ line argument to IRQ_CONNECT(), which should ease CMSIS integration. 2) The vector table itself is now generated, which lets us place interrupts directly into the vector table without having to hard-code them. This is a feature we have long enjoyed on x86 and will enable 'direct' interrupts. 3) More code is common, requiring less arch-specific code to support. This patch introduces the common code for this mechanism. Follow-up patches will enable it on various arches. Issue: ZEP-1038, ZEP-1165 Change-Id: I9acd6e0de8b438fa9293f2e00563628f7510168a Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-09 09:16:29 +08:00
#include <sw_isr_table.h>
#include <arch/cpu.h>
#if defined(CONFIG_GEN_SW_ISR_TABLE) && defined(CONFIG_GEN_IRQ_VECTOR_TABLE)
#define ISR_WRAPPER (&_isr_wrapper)
#else
#define ISR_WRAPPER NULL
#endif
gen_isr_tables: apply offset to irq parameter The interrupts would be placed at incorrect offsets on systems where some interrupt vectors are reserved for exceptions, such as ARC. Change-Id: I5b1f00eb9e8aecb84ae66e3d0461a734ffb5fbe6 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-14 01:56:25 +08:00
/* There is an additional member at the end populated by the linker script
* which indicates the number of interrupts specified
*/
struct int_list_header {
void *spurious_ptr;
void *handler_ptr;
arch: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. There are few places we dont convert over to the new types because of compatiability with ext/HALs or for ease of transition at this point. Fixup a few of the PRI formatters so we build with newlib. Jira: ZEP-2051 Change-Id: I7d2d3697cad04f20aaa8f6e77228f502cd9c8286 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 02:30:33 +08:00
u32_t table_size;
u32_t offset;
gen_isr_tables: apply offset to irq parameter The interrupts would be placed at incorrect offsets on systems where some interrupt vectors are reserved for exceptions, such as ARC. Change-Id: I5b1f00eb9e8aecb84ae66e3d0461a734ffb5fbe6 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-14 01:56:25 +08:00
};
gen_isr_tables: New static interrupt build mechanism This is a new mechanism for generating interrupt tables which will be useful on many architectures. It replaces the old linker-based mechanism for creating these tables and has a couple advantages: 1) It is now possible to use enums as the IRQ line argument to IRQ_CONNECT(), which should ease CMSIS integration. 2) The vector table itself is now generated, which lets us place interrupts directly into the vector table without having to hard-code them. This is a feature we have long enjoyed on x86 and will enable 'direct' interrupts. 3) More code is common, requiring less arch-specific code to support. This patch introduces the common code for this mechanism. Follow-up patches will enable it on various arches. Issue: ZEP-1038, ZEP-1165 Change-Id: I9acd6e0de8b438fa9293f2e00563628f7510168a Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-09 09:16:29 +08:00
/* These values are not included in the resulting binary, but instead form the
* header of the initList section, which is used by gen_isr_tables.py to create
* the vector and sw isr tables,
*/
gen_isr_tables: apply offset to irq parameter The interrupts would be placed at incorrect offsets on systems where some interrupt vectors are reserved for exceptions, such as ARC. Change-Id: I5b1f00eb9e8aecb84ae66e3d0461a734ffb5fbe6 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-14 01:56:25 +08:00
_GENERIC_SECTION(.irq_info) struct int_list_header _iheader = {
.spurious_ptr = &_irq_spurious,
.handler_ptr = ISR_WRAPPER,
.table_size = IRQ_TABLE_SIZE,
.offset = CONFIG_GEN_IRQ_START_VECTOR,
};
gen_isr_tables: New static interrupt build mechanism This is a new mechanism for generating interrupt tables which will be useful on many architectures. It replaces the old linker-based mechanism for creating these tables and has a couple advantages: 1) It is now possible to use enums as the IRQ line argument to IRQ_CONNECT(), which should ease CMSIS integration. 2) The vector table itself is now generated, which lets us place interrupts directly into the vector table without having to hard-code them. This is a feature we have long enjoyed on x86 and will enable 'direct' interrupts. 3) More code is common, requiring less arch-specific code to support. This patch introduces the common code for this mechanism. Follow-up patches will enable it on various arches. Issue: ZEP-1038, ZEP-1165 Change-Id: I9acd6e0de8b438fa9293f2e00563628f7510168a Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-09 09:16:29 +08:00
/* These are placeholder tables. They will be replaced by the real tables
* generated by gen_isr_tables.py.
*/
/* Some arches don't use a vector table, they have a common exception entry
* point for all interrupts. Don't generate a table in this case.
*/
#ifdef CONFIG_GEN_IRQ_VECTOR_TABLE
arch: convert to using newly introduced integer sized types Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99 integer types. There are few places we dont convert over to the new types because of compatiability with ext/HALs or for ease of transition at this point. Fixup a few of the PRI formatters so we build with newlib. Jira: ZEP-2051 Change-Id: I7d2d3697cad04f20aaa8f6e77228f502cd9c8286 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 02:30:33 +08:00
u32_t __irq_vector_table _irq_vector_table[IRQ_TABLE_SIZE] = {
gen_isr_tables: New static interrupt build mechanism This is a new mechanism for generating interrupt tables which will be useful on many architectures. It replaces the old linker-based mechanism for creating these tables and has a couple advantages: 1) It is now possible to use enums as the IRQ line argument to IRQ_CONNECT(), which should ease CMSIS integration. 2) The vector table itself is now generated, which lets us place interrupts directly into the vector table without having to hard-code them. This is a feature we have long enjoyed on x86 and will enable 'direct' interrupts. 3) More code is common, requiring less arch-specific code to support. This patch introduces the common code for this mechanism. Follow-up patches will enable it on various arches. Issue: ZEP-1038, ZEP-1165 Change-Id: I9acd6e0de8b438fa9293f2e00563628f7510168a Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-09 09:16:29 +08:00
[0 ...(IRQ_TABLE_SIZE - 1)] = 0xabababab,
};
#endif
/* If there are no interrupts at all, or all interrupts are of the 'direct'
* type and bypass the _sw_isr_table, then do not generate one.
*/
#ifdef CONFIG_GEN_SW_ISR_TABLE
struct _isr_table_entry __sw_isr_table _sw_isr_table[IRQ_TABLE_SIZE] = {
[0 ...(IRQ_TABLE_SIZE - 1)] = {(void *)0xcdcdcdcd, (void *)0xcdcdcdcd},
};
#endif
/* Linker needs this */
GEN_ABS_SYM_BEGIN(isr_tables_syms)
GEN_ABSOLUTE_SYM(__ISR_LIST_SIZEOF, sizeof(struct _isr_list));
GEN_ABS_SYM_END