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zephyr/boards/riscv/hifive1_revb/hifive1_revb_defconfig

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riscv: freedom: rename RISCV32 to RISCV This code is common to 32- and 64-bit builds. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-07-19 11:05:53 +08:00
CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM=y
CONFIG_SOC_RISCV_SIFIVE_FREEDOM=y
boards/riscv32: Add support for the HiFive1 Rev B The HiFive1 Rev B adds the following features to the original HiFive1: - A second UART peripheral 'uart_1' - A hardware I2C peripheral 'i2c_0' - Segger J-Link OB - An ESP32-WROOM attached to the 'spi_1' peripheral bus Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-20 00:36:55 +08:00
CONFIG_BOARD_HIFIVE1_REVB=y
CONFIG_RISCV_MACHINE_TIMER=y
CONFIG_PLIC=y
CONFIG_GPIO=y
CONFIG_GPIO_SIFIVE=y
boards: FE310-based boards: transition to pinctrl driver This commit makes the transition from the pinmux driver to the pinctrl driver. It also modifies UART, SPI and I2C drivers used in FE310-based boards to use the new pinctrl API. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-03-22 16:38:57 +08:00
CONFIG_PINCTRL=y
boards/riscv32: Add support for the HiFive1 Rev B The HiFive1 Rev B adds the following features to the original HiFive1: - A second UART peripheral 'uart_1' - A hardware I2C peripheral 'i2c_0' - Segger J-Link OB - An ESP32-WROOM attached to the 'spi_1' peripheral bus Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-20 00:36:55 +08:00
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_SIFIVE=y
CONFIG_UART_SIFIVE_PORT_0=y
CONFIG_UART_CONSOLE=y
boards: hifive1_revb: add support for memory protection features Add this board to E31 core family. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
2020-10-29 15:26:27 +08:00
CONFIG_CORE_E31=y