zephyr/dts/arm/ti/mem.h

/*
 * Copyright (c) 2017 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef __DT_BINDING_TI_MEM_H
#define __DT_BINDING_TI_MEM_H

#define __SIZE_K(x) (x * 1024)

#if defined(CONFIG_SOC_CC3220SF)
#define DT_SFLASH_SIZE		__SIZE_K(1024)
#define DT_FLASH_SIZE		__SIZE_K(1024)
#define DT_SRAM_SIZE		__SIZE_K(256)
#define DT_SRAM_START		0x20000000
#elif defined(CONFIG_SOC_MSP432P401R)
#define DT_FLASH_SIZE		__SIZE_K(256)
#define DT_SRAM_SIZE		__SIZE_K(64)
#define DT_SRAM_START		0x20000000
#else
#error "Flash and RAM sizes not defined for this chip"
#endif

#endif /* __DT_BINDING_TI_MEM_H */
license: add missing licenses and copyright We were missing license boilerplate in many files, add them Jira: ZEP-1464 Signed-off-by: Anas Nashif <anas.nashif@intel.com> 2017-06-08 22:24:51 +08:00			`/*`
			`* Copyright (c) 2017 Linaro Limited`
			`*`
			`* SPDX-License-Identifier: Apache-2.0`
			`*/`

cc3200: Make use of mem.h file in soc dtsi file. This in preparation for adding a cc3220sf DTS file, which has a different address for sram0 than the cc3200. Also moved baud-rate out of soc dtsi file to board dts. Jira: JEP-1958 Change-Id: I641452c0a8a6d1ad4424e132d6ef2de71d8545b4 Signed-off-by: Gil Pitney <gil.pitney@linaro.org> 2017-04-19 05:18:50 +08:00			`#ifndef __DT_BINDING_TI_MEM_H`
			`#define __DT_BINDING_TI_MEM_H`

			`#define __SIZE_K(x) (x * 1024)`

cc3200: Remove TI cc3200 SOC and LaunchXL board support Per ZEP-1958, Phase 2 of adding CC3220sf LaunchXL support, was to "deprecate the CC3200 launchxl support in Zephyr (redundant to the CC3220)." Effectively, the CC3220 SOC replaces the CC3200. This patch removes the following: * the imported CC3200 SDK * CC3200 SOC, board, DTS files. * adjusts other files where cc3200 was mentioned. Also, it fixes explicit references to CC3200 in generic CC32xx driver files. Jira: ZEP-1958 Signed-off-by: Gil Pitney <gil.pitney@linaro.org> 2017-08-15 09:26:39 +08:00			`#if defined(CONFIG_SOC_CC3220SF)`
boards: Add support for the CC3220SF_LAUNCHXL board CC3220SF_LAUNCHXL effectively replaces the CC3200_LAUNCHXL, with support for the CC3220SF SoC, which is an update for the CC3200 SoC. This is supported by the Texas Instruments CC3220 SDK. Jira: ZEP-1958 Change-Id: I2484d3ee87b7f909c783597d95128f2b45db36f2 Signed-off-by: Gil Pitney <gil.pitney@linaro.org> 2017-04-19 05:43:44 +08:00			`#define DT_SFLASH_SIZE __SIZE_K(1024)`
			`#define DT_FLASH_SIZE __SIZE_K(1024)`
			`#define DT_SRAM_SIZE __SIZE_K(256)`
			`#define DT_SRAM_START 0x20000000`
arch: arm: soc: ti_simplelink: Add MSP432P401R SoC This patch adds SoC support for TI SimpleLink family MSP432P401R. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 2017-07-22 14:10:56 +08:00			`#elif defined(CONFIG_SOC_MSP432P401R)`
			`#define DT_FLASH_SIZE __SIZE_K(256)`
			`#define DT_SRAM_SIZE __SIZE_K(64)`
			`#define DT_SRAM_START 0x20000000`
cc3200: Make use of mem.h file in soc dtsi file. This in preparation for adding a cc3220sf DTS file, which has a different address for sram0 than the cc3200. Also moved baud-rate out of soc dtsi file to board dts. Jira: JEP-1958 Change-Id: I641452c0a8a6d1ad4424e132d6ef2de71d8545b4 Signed-off-by: Gil Pitney <gil.pitney@linaro.org> 2017-04-19 05:18:50 +08:00			`#else`
			`#error "Flash and RAM sizes not defined for this chip"`
			`#endif`

			`#endif /* __DT_BINDING_TI_MEM_H */`