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zephyr/dts/riscv32/rv32m1_ri5cy.dtsi

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soc: riscv32: add RV32M1 SoC as openisa_rv32m1 The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V 32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC enablement for the RISC-V cores: - basic dtsi, to be extended as additional drivers are added - SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY - system timer driver for RI5CY, based on LPTMR0 peripheral The timer driver will be generalized a bit soon once proper multi-level interrupt support is available. Emphasis is on supporting the RI5CY core as the more capable of the two; the ZERO-RISCY SoC definitions are a good starting point, but additional work setting up a dtsi and initial drivers is needed to support that core. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-25 17:40:57 +08:00
/*
* Copyright 2018 Foundries.io Ltd
* SPDX-License-Identifier: Apache-2.0
*/
interrupt_controller: RV32M1: add intmux driver / DT bindings Add a level 2 interrupt controller for the RV32M1 SoC. This uses the INTMUX peripheral. As a first customer, convert the timer driver over to using this, adding nodes for the LPTMR peripherals. This lets users select the timer instance they want to use, and what intmux channel they want to route its interrupt to, using DT overlays. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Mike Scott <mike@foundries.io>
2018-11-25 17:41:38 +08:00
#include <dt-bindings/interrupt-controller/openisa-intmux.h>
soc: riscv32: add RV32M1 SoC as openisa_rv32m1 The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V 32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC enablement for the RISC-V cores: - basic dtsi, to be extended as additional drivers are added - SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY - system timer driver for RI5CY, based on LPTMR0 peripheral The timer driver will be generalized a bit soon once proper multi-level interrupt support is available. Emphasis is on supporting the RI5CY core as the more capable of the two; the ZERO-RISCY SoC definitions are a good starting point, but additional work setting up a dtsi and initial drivers is needed to support that core. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-25 17:40:57 +08:00
/ {
#address-cells = <1>;
#size-cells = <1>;
clock_control: RV32M1: introduce PCC driver / DT bindings Add a Peripheral Clock Controller (PCC) driver. This gates and ungates clocks to various peripherals on the SoC. Signed-off-by: Michael Scott <mike@foundries.io> Signed-off-by: Marti Bolivar <marti@foundries.io>
2018-11-08 02:13:52 +08:00
aliases {
pcc-0 = &pcc0;
pcc-1 = &pcc1;
interrupt_controller: RV32M1: add intmux driver / DT bindings Add a level 2 interrupt controller for the RV32M1 SoC. This uses the INTMUX peripheral. As a first customer, convert the timer driver over to using this, adding nodes for the LPTMR peripherals. This lets users select the timer instance they want to use, and what intmux channel they want to route its interrupt to, using DT overlays. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Mike Scott <mike@foundries.io>
2018-11-25 17:41:38 +08:00
intmux = &intmux;
system-lptmr = &lptmr0;
clock_control: RV32M1: introduce PCC driver / DT bindings Add a Peripheral Clock Controller (PCC) driver. This gates and ungates clocks to various peripherals on the SoC. Signed-off-by: Michael Scott <mike@foundries.io> Signed-off-by: Marti Bolivar <marti@foundries.io>
2018-11-08 02:13:52 +08:00
};
soc: riscv32: add RV32M1 SoC as openisa_rv32m1 The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V 32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC enablement for the RISC-V cores: - basic dtsi, to be extended as additional drivers are added - SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY - system timer driver for RI5CY, based on LPTMR0 peripheral The timer driver will be generalized a bit soon once proper multi-level interrupt support is available. Emphasis is on supporting the RI5CY core as the more capable of the two; the ZERO-RISCY SoC definitions are a good starting point, but additional work setting up a dtsi and initial drivers is needed to support that core. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-25 17:40:57 +08:00
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "riscv";
reg = <0>;
};
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x20000000 0x30000>;
};
clock_control: RV32M1: introduce PCC driver / DT bindings Add a Peripheral Clock Controller (PCC) driver. This gates and ungates clocks to various peripherals on the SoC. Signed-off-by: Michael Scott <mike@foundries.io> Signed-off-by: Marti Bolivar <marti@foundries.io>
2018-11-08 02:13:52 +08:00
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
pcc0: clock-controller@4002b000 {
compatible = "openisa,rv32m1-pcc";
clock-controller;
reg = <0x4002b000 0x200>;
label = "PCC0";
#clock-cells = <1>;
};
pcc1: clock-controller@41027000 {
compatible = "openisa,rv32m1-pcc";
clock-controller;
reg = <0x41027000 0x200>;
label = "PCC1";
#clock-cells = <1>;
};
interrupt_controller: RV32M1: add intmux driver / DT bindings Add a level 2 interrupt controller for the RV32M1 SoC. This uses the INTMUX peripheral. As a first customer, convert the timer driver over to using this, adding nodes for the LPTMR peripherals. This lets users select the timer instance they want to use, and what intmux channel they want to route its interrupt to, using DT overlays. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Mike Scott <mike@foundries.io>
2018-11-25 17:41:38 +08:00
event: interrupt-controller@e0041000 {
compatible = "openisa,rv32m1-event-unit";
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xe0041000 0x88>;
};
intmux: interrupt-controller@4004f000 {
compatible = "openisa,rv32m1-intmux";
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&event>;
interrupts = <INTMUX_CH0_IRQ>, <INTMUX_CH1_IRQ>, <INTMUX_CH2_IRQ>, <INTMUX_CH3_IRQ>, <INTMUX_CH4_IRQ>, <INTMUX_CH5_IRQ>, <INTMUX_CH6_IRQ>, <INTMUX_CH7_IRQ>;
reg = <0x4004f000 0x20>;
clocks = <&pcc0 0x13c>;
label = "INTMUX0";
};
/*
* INTMUX channels below are somewhat arbitrary.
*
* The system timer (assumed at LPTMR0) is placed on channel 0,
* and peripherals are in channel 1. This can be overridden with
* overlays, e.g. to manage IRQ priorities, and it'll will Just
* Work, but using fewer channels here allows disabling unused
* ones in Kconfig, making the binary smaller.
*
* Each enabled channel requires 256 bytes in _sw_isr_table,
* so the savings for disabling channels can add up.
*/
lptmr0: timer@40032000 {
compatible = "openisa,rv32m1-lptmr";
reg = <0x40032000 0x10>;
interrupt-parent = <&intmux>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 7)>;
label = "LPTMR_0";
};
lptmr1: timer@40033000 {
compatible = "openisa,rv32m1-lptmr";
reg = <0x40033000 0x10>;
interrupt-parent = <&intmux>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 8)>;
label = "LPTMR_1";
};
lptmr2: timer@4102b000 {
compatible = "openisa,rv32m1-lptmr";
reg = <0x4102b000 0x10>;
interrupt-parent = <&intmux>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 22)>;
label = "LPTMR_2";
};
clock_control: RV32M1: introduce PCC driver / DT bindings Add a Peripheral Clock Controller (PCC) driver. This gates and ungates clocks to various peripherals on the SoC. Signed-off-by: Michael Scott <mike@foundries.io> Signed-off-by: Marti Bolivar <marti@foundries.io>
2018-11-08 02:13:52 +08:00
};
soc: riscv32: add RV32M1 SoC as openisa_rv32m1 The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V 32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC enablement for the RISC-V cores: - basic dtsi, to be extended as additional drivers are added - SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY - system timer driver for RI5CY, based on LPTMR0 peripheral The timer driver will be generalized a bit soon once proper multi-level interrupt support is available. Emphasis is on supporting the RI5CY core as the more capable of the two; the ZERO-RISCY SoC definitions are a good starting point, but additional work setting up a dtsi and initial drivers is needed to support that core. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-25 17:40:57 +08:00
};