zephyr/soc/riscv/riscv-privilege/sifive-freedom/CMakeLists.txt

# SPDX-License-Identifier: Apache-2.0

zephyr_sources()
zephyr_sources(fe310_clock.c)
license: cleanup: add SPDX Apache-2.0 license identifier Update the files which contain no license information with the 'Apache-2.0' SPDX license identifier. Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of Zephyr, which is Apache version 2. Signed-off-by: Anas Nashif <anas.nashif@intel.com> 2019-04-06 21:08:09 +08:00			`# SPDX-License-Identifier: Apache-2.0`

riscv32: riscv-privilege: Microsemi Mi-V support This commit adds support for Microsemi Mi-V RISC-V softcore CPU running on the M2GL025 IGLOO2 FPGA development board. signed-off-by: Karol Gugala <kgugala@antmicro.com> 2018-06-11 01:02:14 +08:00			`zephyr_sources()`
soc/riscv32: Make clock init code common to SoC The HiFive1 and HiFive1 Rev B share the same clock initialization code, so put it in soc/riscv32/riscv-privilege/sifive-freedom. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> 2019-03-21 01:22:28 +08:00			`zephyr_sources(fe310_clock.c)`