346 lines
9.6 KiB
C
346 lines
9.6 KiB
C
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/*
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* Copyright (c) 2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT adi_max32_counter
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#include <zephyr/drivers/counter.h>
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#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/irq.h>
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#include <wrap_max32_tmr.h>
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/** MAX32 MCUs does not have multiple channels */
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#define MAX32_TIMER_CH 1U
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struct max32_tmr_data {
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counter_top_callback_t top_callback;
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void *top_user_data;
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uint32_t guard_period;
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};
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struct max32_tmr_ch_data {
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counter_alarm_callback_t callback;
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void *user_data;
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};
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struct max32_tmr_config {
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struct counter_config_info info;
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struct max32_tmr_ch_data *ch_data;
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mxc_tmr_regs_t *regs;
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const struct device *clock;
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struct max32_perclk perclk;
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int clock_source;
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int prescaler;
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void (*irq_func)(const struct device *dev);
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bool wakeup_source;
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};
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static int api_start(const struct device *dev)
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{
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const struct max32_tmr_config *cfg = dev->config;
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Wrap_MXC_TMR_EnableInt(cfg->regs);
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MXC_TMR_Start(cfg->regs);
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return 0;
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}
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static int api_stop(const struct device *dev)
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{
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const struct max32_tmr_config *cfg = dev->config;
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Wrap_MXC_TMR_DisableInt(cfg->regs);
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MXC_TMR_Stop(cfg->regs);
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return 0;
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}
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static int api_get_value(const struct device *dev, uint32_t *ticks)
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{
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const struct max32_tmr_config *cfg = dev->config;
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*ticks = MXC_TMR_GetCount(cfg->regs);
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return 0;
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}
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static int api_set_top_value(const struct device *dev, const struct counter_top_cfg *counter_cfg)
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{
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const struct max32_tmr_config *cfg = dev->config;
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if (counter_cfg->ticks == 0) {
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return -EINVAL;
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}
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if (counter_cfg->ticks != cfg->info.max_top_value) {
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return -ENOTSUP;
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}
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return 0;
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}
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static uint32_t api_get_pending_int(const struct device *dev)
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{
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const struct max32_tmr_config *cfg = dev->config;
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return Wrap_MXC_TMR_GetPendingInt(cfg->regs);
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}
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static uint32_t api_get_top_value(const struct device *dev)
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{
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const struct max32_tmr_config *cfg = dev->config;
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return cfg->info.max_top_value;
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}
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static uint32_t api_get_freq(const struct device *dev)
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{
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const struct max32_tmr_config *cfg = dev->config;
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return cfg->info.freq;
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}
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static int set_cc(const struct device *dev, uint8_t id, uint32_t val, uint32_t flags)
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{
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const struct max32_tmr_config *config = dev->config;
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struct max32_tmr_data *data = dev->data;
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mxc_tmr_regs_t *regs = config->regs;
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bool absolute = flags & COUNTER_ALARM_CFG_ABSOLUTE;
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uint32_t top = api_get_top_value(dev);
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int err = 0;
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uint32_t now;
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uint32_t diff;
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uint32_t max_rel_val = top;
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bool irq_on_late = 0;
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now = MXC_TMR_GetCount(regs);
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MXC_TMR_ClearFlags(regs);
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if (absolute) {
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max_rel_val = top - data->guard_period;
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irq_on_late = flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE;
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} else {
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val = now + val;
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}
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MXC_TMR_SetCompare(regs, val);
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now = MXC_TMR_GetCount(regs);
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diff = (val - now);
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if (diff > max_rel_val) {
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if (absolute) {
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err = -ETIME;
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}
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/* Interrupt is triggered always for relative alarm and
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* for absolute depending on the flag.
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*/
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if (irq_on_late) {
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NVIC_SetPendingIRQ(MXC_TMR_GET_IRQ(MXC_TMR_GET_IDX(regs)));
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} else {
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config->ch_data[id].callback = NULL;
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}
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} else {
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api_start(dev);
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}
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return err;
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}
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static int api_set_alarm(const struct device *dev, uint8_t chan,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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const struct max32_tmr_config *cfg = dev->config;
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struct max32_tmr_ch_data *chdata = &cfg->ch_data[chan];
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if (alarm_cfg->ticks > api_get_top_value(dev)) {
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return -EINVAL;
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}
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if (chdata->callback) {
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return -EBUSY;
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}
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chdata->callback = alarm_cfg->callback;
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chdata->user_data = alarm_cfg->user_data;
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return set_cc(dev, chan, alarm_cfg->ticks, alarm_cfg->flags);
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}
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static int api_cancel_alarm(const struct device *dev, uint8_t chan)
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{
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const struct max32_tmr_config *cfg = dev->config;
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MXC_TMR_Stop(cfg->regs);
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MXC_TMR_SetCount(cfg->regs, 0);
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MXC_TMR_SetCompare(cfg->regs, cfg->info.max_top_value);
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Wrap_MXC_TMR_DisableInt(cfg->regs);
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cfg->ch_data[chan].callback = NULL;
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return 0;
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}
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static uint32_t api_get_guard_period(const struct device *dev, uint32_t flags)
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{
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struct max32_tmr_data *data = dev->data;
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ARG_UNUSED(flags);
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return data->guard_period;
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}
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static int api_set_guard_period(const struct device *dev, uint32_t ticks, uint32_t flags)
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{
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struct max32_tmr_data *data = dev->data;
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ARG_UNUSED(flags);
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if (ticks > api_get_top_value(dev)) {
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return -EINVAL;
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}
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data->guard_period = ticks;
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return 0;
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}
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static void max32_alarm_irq_handle(const struct device *dev, uint32_t id)
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{
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const struct max32_tmr_config *cfg = dev->config;
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struct max32_tmr_ch_data *chdata;
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counter_alarm_callback_t cb;
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chdata = &cfg->ch_data[id];
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cb = chdata->callback;
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chdata->callback = NULL;
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if (cb) {
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cb(dev, id, MXC_TMR_GetCount(cfg->regs), chdata->user_data);
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}
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}
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static void counter_max32_isr(const struct device *dev)
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{
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const struct max32_tmr_config *cfg = dev->config;
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struct max32_tmr_data *data = dev->data;
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MXC_TMR_ClearFlags(cfg->regs);
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Wrap_MXC_TMR_ClearWakeupFlags(cfg->regs);
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max32_alarm_irq_handle(dev, 0);
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if (data->top_callback) {
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data->top_callback(dev, data->top_user_data);
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}
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}
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static int max32_counter_init(const struct device *dev)
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{
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int ret = 0;
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const struct max32_tmr_config *cfg = dev->config;
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mxc_tmr_regs_t *regs = cfg->regs;
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wrap_mxc_tmr_cfg_t tmr_cfg;
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int prescaler_index;
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prescaler_index = LOG2(cfg->prescaler);
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if (prescaler_index == 0) {
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tmr_cfg.pres = TMR_PRES_1; /* TMR_PRES_1 is 0 */
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} else {
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/* TMR_PRES_2 is 1<<X */
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tmr_cfg.pres = TMR_PRES_2 + (prescaler_index - 1);
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}
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tmr_cfg.mode = TMR_MODE_COMPARE;
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tmr_cfg.cmp_cnt = cfg->info.max_top_value;
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tmr_cfg.bitMode = 0; /* Timer Mode 32 bit */
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tmr_cfg.pol = 0;
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tmr_cfg.clock = Wrap_MXC_TMR_GetClockIndex(cfg->clock_source);
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if (tmr_cfg.clock < 0) {
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return -ENOTSUP;
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}
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MXC_TMR_Shutdown(regs);
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/* enable clock */
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ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk);
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if (ret) {
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return ret;
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}
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ret = Wrap_MXC_TMR_Init(regs, &tmr_cfg);
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if (ret != E_NO_ERROR) {
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return ret;
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}
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/* Set preload and actually pre-load the counter */
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MXC_TMR_SetCompare(regs, cfg->info.max_top_value);
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cfg->irq_func(dev);
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if (cfg->wakeup_source) {
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/* Clear Wakeup status */
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MXC_LP_ClearWakeStatus();
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/* Enable Timer wake-up source */
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Wrap_MXC_TMR_EnableWakeup(regs, &tmr_cfg);
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}
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return 0;
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}
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static const struct counter_driver_api counter_max32_driver_api = {
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.start = api_start,
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.stop = api_stop,
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.get_value = api_get_value,
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.set_top_value = api_set_top_value,
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.get_pending_int = api_get_pending_int,
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.get_top_value = api_get_top_value,
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.get_freq = api_get_freq,
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.set_alarm = api_set_alarm,
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.cancel_alarm = api_cancel_alarm,
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.get_guard_period = api_get_guard_period,
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.set_guard_period = api_set_guard_period,
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};
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#define TIMER(_num) DT_INST_PARENT(_num)
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#define MAX32_TIM(idx) ((mxc_tmr_regs_t *)DT_REG_ADDR(TIMER(idx)))
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#define COUNTER_MAX32_DEFINE(_num) \
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static struct max32_tmr_ch_data counter##_num##_ch_data[MAX32_TIMER_CH]; \
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static void max32_tmr_irq_init_##_num(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_IRQN(TIMER(_num)), DT_IRQ(TIMER(_num), priority), \
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counter_max32_isr, DEVICE_DT_INST_GET(_num), 0); \
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irq_enable(DT_IRQN(TIMER(_num))); \
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}; \
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static const struct max32_tmr_config max32_tmr_config_##_num = { \
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.info = \
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{ \
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.max_top_value = WRAP_MXC_IS_32B_TIMER(MAX32_TIM(_num)) \
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? UINT32_MAX \
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: UINT16_MAX, \
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.freq = ADI_MAX32_GET_PRPH_CLK_FREQ( \
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DT_PROP(TIMER(_num), clock_source)) / \
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DT_PROP(TIMER(_num), prescaler), \
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.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
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.channels = MAX32_TIMER_CH, \
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}, \
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.regs = (mxc_tmr_regs_t *)DT_REG_ADDR(TIMER(_num)), \
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.clock = DEVICE_DT_GET(DT_CLOCKS_CTLR(TIMER(_num))), \
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.perclk.bus = DT_CLOCKS_CELL(TIMER(_num), offset), \
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.perclk.bit = DT_CLOCKS_CELL(TIMER(_num), bit), \
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.clock_source = DT_PROP(TIMER(_num), clock_source), \
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.prescaler = DT_PROP(TIMER(_num), prescaler), \
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.irq_func = max32_tmr_irq_init_##_num, \
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.ch_data = counter##_num##_ch_data, \
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.wakeup_source = DT_PROP(TIMER(_num), wakeup_source), \
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}; \
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static struct max32_tmr_data max32_tmr_data##_num; \
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DEVICE_DT_INST_DEFINE(_num, &max32_counter_init, NULL, &max32_tmr_data##_num, \
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&max32_tmr_config_##_num, PRE_KERNEL_1, \
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CONFIG_COUNTER_INIT_PRIORITY, &counter_max32_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(COUNTER_MAX32_DEFINE)
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