77 lines
1.8 KiB
Plaintext
77 lines
1.8 KiB
Plaintext
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# Kconfig.defconfig: RV32M1 SoC RISC-V core default configuration values
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#
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# Copyright (c) 2018 Foundries.io Ltd
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#
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# SPDX-License-Identifier: Apache-2.0
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if SOC_OPENISA_RV32M1_RISCV32
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config SOC
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string
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default "openisa_rv32m1"
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config NUM_IRQS
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int
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default 32
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config XIP
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bool
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default y
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config RISCV_GENERIC_TOOLCHAIN
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bool
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default n
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config RISCV_SOC_CONTEXT_SAVE
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bool
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default y if SOC_OPENISA_RV32M1_RI5CY
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config RISCV_SOC_INTERRUPT_INIT
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bool
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default y
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# We need to disable the watchdog out of reset, as it's enabled by
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# default. Use the WDOG_INIT hook for doing that.
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config WDOG_INIT
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def_bool y
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# Built-in flash allocated to each chip. This configuration
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# assumes the Arm cores are disabled, as these base addresses
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# contain the Arm core vector tables if they are used.
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config RISCV32_RV32M1_ROM_BASE_ADDR
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hex
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default 0x00000000 if SOC_OPENISA_RV32M1_RI5CY
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default 0x01000000 if SOC_OPENISA_RV32M1_ZERO_RISCY
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config RISCV32_RV32M1_ROM_SIZE
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hex
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default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY
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default 0x0003FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY
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config RISCV32_RV32M1_RAM_BASE_ADDR
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hex
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default 0x20000000 if SOC_OPENISA_RV32M1_RI5CY
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default 0x09000000 if SOC_OPENISA_RV32M1_ZERO_RISCY
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config RISCV32_RV32M1_RAM_SIZE
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hex
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default 0x00030000 if SOC_OPENISA_RV32M1_RI5CY
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default 0x00020000 if SOC_OPENISA_RV32M1_ZERO_RISCY
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# The event unit looks for vector tables at the end of each core's
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# flash space. These vector tables are not relocatable.
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config RISCV32_RV32M1_VECTOR_BASE_ADDR
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hex
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default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY
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default 0x0103FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY
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config RISCV32_RV32M1_VECTOR_SIZE
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hex
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default 0x100
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default 8000000 if SOC_OPENISA_RV32M1_RI5CY # SIRC at 8MHz
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endif # SOC_OPENISA_RV32M1_RISCV32
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