2022-02-14 21:22:29 +08:00
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/*
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* Xilinx Processor System MIO / EMIO GPIO controller driver
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*
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* Driver private data declarations, parent (IRQ handler) module
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*
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* Copyright (c) 2022, Weidmueller Interface GmbH & Co. KG
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_H_
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#define _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_H_
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/* Type definitions */
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/* IRQ handler function type */
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typedef void (*gpio_xlnx_ps_config_irq_t)(const struct device *dev);
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/**
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* @brief Run-time modifiable device data structure.
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*
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* This struct contains all data of the PS GPIO controller parent
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* (IRQ handler) which is modifiable at run-time.
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*/
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struct gpio_xlnx_ps_dev_data {
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struct gpio_driver_data common;
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};
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/**
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* @brief Constant device configuration data structure.
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*
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* This struct contains all data of the PS GPIO controller parent
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* which is required for proper operation (such as base memory
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* addresses, references to all associated banks etc.) which don't
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* have to and therefore cannot be modified at run-time.
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*/
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struct gpio_xlnx_ps_dev_cfg {
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struct gpio_driver_config common;
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uint32_t base_addr;
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2022-08-20 21:40:04 +08:00
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const struct device *const *bank_devices;
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2022-02-14 21:22:29 +08:00
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uint32_t num_banks;
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gpio_xlnx_ps_config_irq_t config_func;
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};
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#endif /* _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_H_ */
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