87 lines
2.4 KiB
C
87 lines
2.4 KiB
C
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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (C) 2022-2023, Intel Corporation
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*
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*/
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
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#include <zephyr/logging/log.h>
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#include "clock_control_agilex5_ll.h"
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#define DT_DRV_COMPAT intel_agilex5_clock
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LOG_MODULE_REGISTER(clock_control_agilex5, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
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struct clock_control_config {
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DEVICE_MMIO_ROM;
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};
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struct clock_control_data {
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DEVICE_MMIO_RAM;
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};
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static int clock_init(const struct device *dev)
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{
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DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
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/* Initialize the low layer clock driver */
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clock_agilex5_ll_init(DEVICE_MMIO_GET(dev));
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LOG_INF("Intel Agilex5 clock driver initialized!");
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return 0;
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}
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static int clock_get_rate(const struct device *dev, clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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ARG_UNUSED(dev);
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switch ((intptr_t)sub_system) {
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case INTEL_SOCFPGA_CLOCK_MPU:
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*rate = get_mpu_clk();
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break;
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case INTEL_SOCFPGA_CLOCK_WDT:
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*rate = get_wdt_clk();
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break;
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case INTEL_SOCFPGA_CLOCK_UART:
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*rate = get_uart_clk();
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break;
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case INTEL_SOCFPGA_CLOCK_MMC:
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*rate = get_mmc_clk();
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break;
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case INTEL_SOCFPGA_CLOCK_TIMER:
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*rate = get_timer_clk();
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break;
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default:
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LOG_ERR("Clock ID %ld is not supported\n", (intptr_t)sub_system);
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return -ENOTSUP;
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}
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return 0;
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}
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static const struct clock_control_driver_api clock_api = {.get_rate = clock_get_rate};
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#define CLOCK_CONTROL_DEVICE(_inst) \
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\
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static struct clock_control_data clock_control_data_##_inst; \
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\
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static const struct clock_control_config clock_control_config_##_inst = { \
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DEVICE_MMIO_ROM_INIT(DT_DRV_INST(_inst)), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(_inst, clock_init, NULL, &clock_control_data_##_inst, \
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&clock_control_config_##_inst, PRE_KERNEL_1, \
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_api);
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DT_INST_FOREACH_STATUS_OKAY(CLOCK_CONTROL_DEVICE)
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