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zephyr/soc/arm/gigadevice/gd32f4xx/gd32_regs.h

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drivers: clock_control: gd32: initial support This patch adds a clock control driver for GD32 platforms. It is important to note that the driver is only able to handle peripheral clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On some similar platforms (STM32) this task is embedded in the same clock driver, performed at init time but with no options to do any manipulation at runtime via the API calls. The clock control API as-is is really orthogonal to "system clocks", and it is arguably a bad idea to embed system clock init code in a clock control driver. It can be done at SoC level still using Devicetree as a source of hardware description/initial configuration. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-09-04 01:06:27 +08:00
/*
* Copyright (c) 2022, Teslabs Engineering S.L.
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef SOC_ARM_GIGADEVICE_GD32F4XX_GD32_REGS_H_
#define SOC_ARM_GIGADEVICE_GD32F4XX_GD32_REGS_H_
#include <zephyr/sys/util_macro.h>
/* RCU */
#define RCU_CFG0_OFFSET 0x08U
#define RCU_AHB1EN_OFFSET 0x30U
#define RCU_AHB2EN_OFFSET 0x34U
#define RCU_AHB3EN_OFFSET 0x38U
#define RCU_APB1EN_OFFSET 0x40U
#define RCU_APB2EN_OFFSET 0x44U
#define RCU_ADDAPB1EN_OFFSET 0xE4U
#define RCU_CFG0_AHBPSC_POS 4U
#define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
#define RCU_CFG0_APB1PSC_POS 10U
#define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
#define RCU_CFG0_APB2PSC_POS 13U
#define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
#endif /* SOC_ARM_GIGADEVICE_GD32F4XX_GD32_REGS_H_ */