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zephyr/soc/lowrisc/opentitan/soc.c

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soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:18:32 +08:00
/*
* Copyright (c) 2023 Rivos Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
soc: riscv: opentitan: reduce the scope of some definitions Some definitions were only used in soc.c, there's no need to expose them in a public header like soc.h. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-16 21:58:08 +08:00
/* OpenTitan power management regs. */
soc: riscv: riscv-privilege: opentitan: Enable watchdog reset function Adds watchdog reset as a reset source at SoC init. This is achieved by: 1. Writing 0x2 to the RESET_EN bitfield register to indicate watchdog reset is enabled. 2. Writing 0x1 to the CFG_CDC_SYNC register to commit the change. 3. Polling the CFG_CDC_SYNC register until reading 0 to confirm the change has been processed. This patch is part of the OpenTitan watchdog (AON Timer) support patch series. It is needed to ensure that the watchdog reset functionality is enabled. Note that the timer itself is not enabled here, only the reset function. Signed-off-by: Tyler Ng <tkng@rivosinc.com>
2023-05-10 06:37:13 +08:00
#define PWRMGR_BASE (DT_REG_ADDR(DT_NODELABEL(pwrmgr)))
soc: riscv: opentitan: reduce the scope of some definitions Some definitions were only used in soc.c, there's no need to expose them in a public header like soc.h. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-16 21:58:08 +08:00
#define PWRMGR_CFG_CDC_SYNC_REG_OFFSET 0x018
#define PWRMGR_RESET_EN_REG_OFFSET 0x02c
#define PWRMGR_RESET_EN_WDOG_SRC_MASK 0x002
/* Ibex timer registers. */
soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:18:32 +08:00
#define RV_TIMER_BASE (DT_REG_ADDR(DT_NODELABEL(mtimer)))
soc: riscv: opentitan: reduce the scope of some definitions Some definitions were only used in soc.c, there's no need to expose them in a public header like soc.h. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-16 21:58:08 +08:00
#define RV_TIMER_CTRL_REG_OFFSET 0x004
#define RV_TIMER_INTR_ENABLE_REG_OFFSET 0x100
#define RV_TIMER_CFG0_REG_OFFSET 0x10c
#define RV_TIMER_CFG0_PRESCALE_MASK 0xfff
#define RV_TIMER_CFG0_PRESCALE_OFFSET 0
#define RV_TIMER_CFG0_STEP_MASK 0xff
#define RV_TIMER_CFG0_STEP_OFFSET 16
#define RV_TIMER_LOWER0_OFFSET 0x110
#define RV_TIMER_COMPARE_LOWER0_OFFSET 0x118
soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:18:32 +08:00
soc: lowrisc: move init code from SYS_INIT to hooks Replace SYS_INIT with SoC hooks and adapt SoC init code Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-10 21:42:37 +08:00
void soc_early_init_hook(void)
soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:18:32 +08:00
{
soc: riscv: riscv-privilege: opentitan: Enable watchdog reset function Adds watchdog reset as a reset source at SoC init. This is achieved by: 1. Writing 0x2 to the RESET_EN bitfield register to indicate watchdog reset is enabled. 2. Writing 0x1 to the CFG_CDC_SYNC register to commit the change. 3. Polling the CFG_CDC_SYNC register until reading 0 to confirm the change has been processed. This patch is part of the OpenTitan watchdog (AON Timer) support patch series. It is needed to ensure that the watchdog reset functionality is enabled. Note that the timer itself is not enabled here, only the reset function. Signed-off-by: Tyler Ng <tkng@rivosinc.com>
2023-05-10 06:37:13 +08:00
/* Enable the watchdog reset (bit 1). */
sys_write32(2u, PWRMGR_BASE + PWRMGR_RESET_EN_REG_OFFSET);
/* Write CFG_CDC_SYNC to commit change. */
sys_write32(1u, PWRMGR_BASE + PWRMGR_CFG_CDC_SYNC_REG_OFFSET);
/* Poll CFG_CDC_SYNC register until it reads 0. */
while (sys_read32(PWRMGR_BASE + PWRMGR_CFG_CDC_SYNC_REG_OFFSET)) {
}
soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:18:32 +08:00
/* Initialize the Machine Timer, so it behaves as a regular one. */
sys_write32(1u, RV_TIMER_BASE + RV_TIMER_CTRL_REG_OFFSET);
/* Enable timer interrupts. */
sys_write32(1u, RV_TIMER_BASE + RV_TIMER_INTR_ENABLE_REG_OFFSET);
}