50 lines
1.5 KiB
C
50 lines
1.5 KiB
C
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/*
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* Copyright (c) 2020 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SDRAM_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SDRAM_H_
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/* Number of column address bits */
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#define STM32_FMC_SDRAM_NC_8 0x00000000UL
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#define STM32_FMC_SDRAM_NC_9 0x00000001UL
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#define STM32_FMC_SDRAM_NC_10 0x00000002UL
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#define STM32_FMC_SDRAM_NC_11 0x00000003UL
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/* Number of row address bits */
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#define STM32_FMC_SDRAM_NR_11 0x00000000UL
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#define STM32_FMC_SDRAM_NR_12 0x00000004UL
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#define STM32_FMC_SDRAM_NR_13 0x00000008UL
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/* Memory data bus width. */
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#define STM32_FMC_SDRAM_MWID_8 0x00000000UL
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#define STM32_FMC_SDRAM_MWID_16 0x00000010UL
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#define STM32_FMC_SDRAM_MWID_32 0x00000020UL
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/* Number of internal banks */
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#define STM32_FMC_SDRAM_NB_2 0x00000000UL
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#define STM32_FMC_SDRAM_NB_4 0x00000040UL
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/* CAS Latency */
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#define STM32_FMC_SDRAM_CAS_1 0x00000080UL
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#define STM32_FMC_SDRAM_CAS_2 0x00000100UL
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#define STM32_FMC_SDRAM_CAS_3 0x00000180UL
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/* SDRAM clock configuration */
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#define STM32_FMC_SDRAM_SDCLK_DISABLE 0x00000000UL
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#define STM32_FMC_SDRAM_SDCLK_PERIOD_2 0x00000800UL
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#define STM32_FMC_SDRAM_SDCLK_PERIOD_3 0x00000C00UL
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/* Burst read */
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#define STM32_FMC_SDRAM_RBURST_DISABLE 0x00000000UL
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#define STM32_FMC_SDRAM_RBURST_ENABLE 0x00001000UL
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/* Read pipe */
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#define STM32_FMC_SDRAM_RPIPE_0 0x00000000UL
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#define STM32_FMC_SDRAM_RPIPE_1 0x00002000UL
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#define STM32_FMC_SDRAM_RPIPE_2 0x00004000UL
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#endif
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